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authorRobert Norton2018-05-09 17:49:12 +0100
committerRobert Norton2018-05-09 17:49:12 +0100
commit710ae06814ca26797a9120f2ecd1d69e0074b32b (patch)
tree4ea81f51d80438581c12cce029fbf4096501e25f /riscv
parenta2256e805507a1a6511b6088c757ff500b27b957 (diff)
remove redundant cloc targets.
Diffstat (limited to 'riscv')
-rw-r--r--riscv/Makefile3
1 files changed, 0 insertions, 3 deletions
diff --git a/riscv/Makefile b/riscv/Makefile
index 3cd235a7..11cc7731 100644
--- a/riscv/Makefile
+++ b/riscv/Makefile
@@ -38,9 +38,6 @@ riscv.lem: $(SAIL_SRCS) Makefile
LOC_FILES:=$(SAIL_SRCS) main.sail
include ../etc/loc.mk
-cloc: $(LOC_FILES)
- cloc --by-file --force-lang C,sail $^
-
clean:
-rm -rf riscv _sbuild
-rm -f riscv.lem riscv_types.lem