diff options
| author | Prashanth Mundkur | 2018-04-18 17:14:32 -0700 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-04-18 17:14:32 -0700 |
| commit | 70d7d17a1ffe0b4ca58a0c65792a48e4232d432f (patch) | |
| tree | 32027d28b894974af41f044317212cb97929f30d /riscv | |
| parent | ae7fbb4ce5f5e52ec39ca17b152db63bbd0cfc69 (diff) | |
Remove obsolete comment.
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/riscv_sys.sail | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/riscv/riscv_sys.sail b/riscv/riscv_sys.sail index fc58d72e..10abeaab 100644 --- a/riscv/riscv_sys.sail +++ b/riscv/riscv_sys.sail @@ -330,7 +330,6 @@ bitfield Sinterrupts : bits(64) = { /* Provides the sip read view of mip as delegated by mideleg. */ function lower_mip(m : Minterrupts, d : Minterrupts) -> Sinterrupts = { let s : Sinterrupts = Mk_Sinterrupts(EXTZ(0b0)); - /* M-mode interrupts delegated to S-mode should appear as S-mode interrupts */ let s = update_SEI(s, m.SEI() & d.SEI()); let s = update_STI(s, m.STI() & d.STI()); let s = update_SSI(s, m.SSI() & d.SSI()); |