Some more riscv trace log tweaking for spike compatibility.

2 files changed, 16 insertions, 5 deletions

diff --git a/riscv/riscv_step.sail b/riscv/riscv_step.sail
index de823f53..acbab1f6 100644
--- a/riscv/riscv_step.sail
+++ b/riscv/riscv_step.sail
@@ -42,9 +42,8 @@ function fetch() -> FetchResult = {
 }
 
 /* returns whether an instruction was retired */
-val step : unit -> bool effect {barr, eamem, escape, exmem, rmem, rreg, wmv, wreg}
-function step() = {
-  let step_no = unsigned(minstret);
+val step : int -> bool effect {barr, eamem, escape, exmem, rmem, rreg, wmv, wreg}
+function step(step_no) = {
   match curInterrupt(mip, mie, mideleg) {
     Some(intr, priv) => {
       print_bits("Handling interrupt: ", intr);
@@ -94,13 +93,16 @@ val loop : unit -> unit effect {barr, eamem, escape, exmem, rmem, rreg, wmv, wre
 function loop () = {
   let insns_per_tick = plat_insns_per_tick();
   i : int = 0;
+  step_no : int = 0;
   while true do {
     tick_clock();
     minstret_written = false;     /* see note for minstret */
-    let retired = step();
+    let retired = step(step_no);
     PC = nextPC;
     if retired then retire_instruction();
 
+    step_no = step_no + 1;
+
     /* check htif exit */
     if htif_done then {
       let exit_val = unsigned(htif_exit_code);
diff --git a/riscv/riscv_sys.sail b/riscv/riscv_sys.sail
index 7d60f0a1..506f0079 100644
--- a/riscv/riscv_sys.sail
+++ b/riscv/riscv_sys.sail
@@ -613,7 +613,8 @@ function is_CSR_defined (csr : bits(12), p : Privilege) -> bool =
     0x344 => p == Machine, // mip
 
     0x3A0 => p == Machine, // pmpcfg0
-    0x3B0 => p == Machine, // pmpaddr0
+    0x3B0 => false, // (Disabled for Spike compatibility)
+//  0x3B0 => p == Machine, // pmpaddr0
 
     /* supervisor mode: trap setup */
     0x100 => p == Machine | p == Supervisor, // sstatus
@@ -786,6 +787,8 @@ function handle_trap(del_priv : Privilege, intr : bool, c : exc_code, pc : xlenb
 
        cur_privilege   = del_priv;
 
+       print("CSR mstatus <- " ^ BitStr(mstatus.bits()) ^ " (input: " ^ BitStr(mstatus.bits()) ^ ")"); // Spike compatible log
+
        match tvec_addr(mtvec, mcause) {
          Some(epc) => epc,
          None()    => internal_error("Invalid mtvec mode")
@@ -807,6 +810,8 @@ function handle_trap(del_priv : Privilege, intr : bool, c : exc_code, pc : xlenb
 
        cur_privilege   = del_priv;
 
+       print("CSR mstatus <- " ^ BitStr(mstatus.bits()) ^ " (input: " ^ BitStr(mstatus.bits()) ^ ")"); // Spike compatible log
+
        match tvec_addr(stvec, scause) {
          Some(epc) => epc,
          None()    => internal_error("Invalid stvec mode")
@@ -832,6 +837,8 @@ function handle_exception(cur_priv : Privilege, ctl : ctl_result,
       mstatus->MPIE() = true;
       cur_privilege   = privLevel_of_bits(mstatus.MPP());
       mstatus->MPP()  = privLevel_to_bits(User);
+
+      print("CSR mstatus <- " ^ BitStr(mstatus.bits()) ^ " (input: " ^ BitStr(mstatus.bits()) ^ ")"); // Spike compatible log
       print("ret-ing from " ^ prev_priv ^ " to " ^ cur_privilege);
       mepc
     },
@@ -841,6 +848,8 @@ function handle_exception(cur_priv : Privilege, ctl : ctl_result,
       mstatus->SPIE() = true;
       cur_privilege   = if mstatus.SPP() == true then Supervisor else User;
       mstatus->SPP()  = false;
+
+      print("CSR mstatus <- " ^ BitStr(mstatus.bits()) ^ " (input: " ^ BitStr(mstatus.bits()) ^ ")"); // Spike compatible log
       print("ret-ing from " ^ prev_priv ^ " to " ^ cur_privilege);
       sepc
     }