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authorPrashanth Mundkur2018-10-06 19:42:22 -0700
committerPrashanth Mundkur2018-10-23 15:32:15 -0700
commit666128be44e51d6b781aedb6fdc97cd90fa59c3c (patch)
tree580b6d26752422899a0806a6d9f98971c0013b1c /riscv
parent90b1e6717008f66f2bab6b7da844c4919583fe67 (diff)
RISC-V: fix: sstatus.SD depends on .XS and .FS.
Diffstat (limited to 'riscv')
-rw-r--r--riscv/riscv_sys.sail6
1 files changed, 5 insertions, 1 deletions
diff --git a/riscv/riscv_sys.sail b/riscv/riscv_sys.sail
index 59bff606..37c45117 100644
--- a/riscv/riscv_sys.sail
+++ b/riscv/riscv_sys.sail
@@ -375,13 +375,17 @@ function lower_mstatus(m : Mstatus) -> Sstatus = {
}
function lift_sstatus(m : Mstatus, s : Sstatus) -> Mstatus = {
- let m = update_SD(m, s.SD());
// FIXME: This should be parameterized by a platform setting. For now, match spike.
// let m = update_UXL(m, s.UXL());
let m = update_MXR(m, s.MXR());
let m = update_SUM(m, s.SUM());
+
+ // FIXME: Should XS and FS check whether X and F|D are supported in misa?
let m = update_XS(m, s.XS());
let m = update_FS(m, s.FS());
+ let m = update_SD(m, extStatus_of_bits(m.FS()) == Dirty
+ | extStatus_of_bits(m.XS()) == Dirty);
+
let m = update_SPP(m, s.SPP());
let m = update_SPIE(m, s.SPIE());
let m = update_UPIE(m, s.UPIE());