diff options
| author | Prashanth Mundkur | 2018-11-07 14:44:59 -0800 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-11-07 17:15:58 -0800 |
| commit | 5d102f7f4791bb650652835781ec08f3543063f2 (patch) | |
| tree | cd7f835487d8495b8a4a1bfa464a4fcc57a99cdf /riscv | |
| parent | e06619625300a3bbf275f1cae6b327b6447f6625 (diff) | |
RISC-V: fix assembly mappings for lr/sc.
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/riscv.sail | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/riscv.sail b/riscv/riscv.sail index 47d714f5..f9945a4d 100644 --- a/riscv/riscv.sail +++ b/riscv/riscv.sail @@ -811,7 +811,7 @@ function clause execute(LOADRES(aq, rl, rs1, width, rd)) = } mapping clause assembly = LOADRES(aq, rl, rs1, size, rd) - <-> "lr" ^ maybe_aq(aq) ^ maybe_rl(rl) ^ size_mnemonic(size) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) + <-> "lr." ^ size_mnemonic(size) ^ maybe_aq(aq) ^ maybe_rl(rl) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) /* ****************************************************************** */ union clause ast = STORECON : (bool, bool, regbits, regbits, word_width, regbits) @@ -876,7 +876,7 @@ function clause execute (STORECON(aq, rl, rs2, rs1, width, rd)) = { } } -mapping clause assembly = STORECON(aq, rl, rs2, rs1, size, rd) <-> "sc" ^ maybe_aq(aq) ^ maybe_rl(rl) ^ size_mnemonic(size) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2) +mapping clause assembly = STORECON(aq, rl, rs2, rs1, size, rd) <-> "sc." ^ size_mnemonic(size) ^ maybe_aq(aq) ^ maybe_rl(rl) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2) /* ****************************************************************** */ union clause ast = AMO : (amoop, bool, bool, regbits, regbits, word_width, regbits) |