diff options
| author | Prashanth Mundkur | 2018-05-07 21:15:13 -0700 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-05-07 21:15:13 -0700 |
| commit | 5bf05d7f31b55a1cda9a93261f338adb04208e7d (patch) | |
| tree | 6ef92e43c5d5257b45c4f6e6fa41bc189955fdcd /riscv | |
| parent | e865a47422dc186d9721cb208ebab1f1a7d7624e (diff) | |
Fix another mask computation bug.
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/riscv_vmem.sail | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/riscv/riscv_vmem.sail b/riscv/riscv_vmem.sail index 26282d3e..7fddb047 100644 --- a/riscv/riscv_vmem.sail +++ b/riscv/riscv_vmem.sail @@ -194,7 +194,8 @@ val make_TLB39_Entry : (asid64, bool, vaddr39, paddr39, SV39_PTE, nat, paddr39) function make_TLB39_Entry(asid, global, vAddr, pAddr, pte, level, pteAddr) = { let shift : nat = PAGESIZE_BITS + (level * SV39_LEVEL_BITS); - let vAddrMask : vaddr39 = shiftl(EXTZ(0b1), shift) - 1; + /* fixme hack: use a better idiom for masks */ + let vAddrMask : vaddr39 = shiftl(vAddr ^ vAddr ^ EXTZ(0b1), shift) - 1; let vMatchMask : vaddr39 = ~ (vAddrMask); struct { asid = asid, |