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authorJon French2018-05-23 16:50:28 +0100
committerJon French2018-05-23 16:50:28 +0100
commit5852dbc82a47d6d9671209390613b30e953ca208 (patch)
tree3632fd0fe4f09fec1eee445ee3e5f96b9a11518f /riscv
parente65dca0c66e3a58c1b295bc0029f519a3eda333d (diff)
restore original riscv main
Diffstat (limited to 'riscv')
-rw-r--r--riscv/main.sail14
1 files changed, 3 insertions, 11 deletions
diff --git a/riscv/main.sail b/riscv/main.sail
index c6fe5d1c..06665cec 100644
--- a/riscv/main.sail
+++ b/riscv/main.sail
@@ -34,24 +34,16 @@ val elf_entry = {
c: "elf_entry"
} : unit -> int
-val main : unit -> unit effect pure //{barr, eamem, escape, exmem, rmem, rreg, wmv, wreg}
+val main : unit -> unit effect {barr, eamem, escape, exmem, rmem, rreg, wmv, wreg}
function main () = {
- print(assembly(ITYPE(0b000000000000, 0b00000, 0b11010, RISCV_ADDI)));
- print(assembly(assembly("addi zero, zero, 0x0")));
- print(assembly(assembly("ldu.aq zero, zero, 0x0")));
- print_bits("assembled lui zero, 0x0: ", encdec(assembly("lui zero, 0x0")));
- print_bits("assembled jal zero, 0x123456 : ", encdec(assembly("jal zero, 0x123456")));
- print(assembly(assembly("beq zero, zero, 0x124")));
- print_bits("assembled beq zero, zero, 0x124 : ", encdec(assembly("beq zero, zero, 0x124")));
- print_bits("assembled fence rw,io : ", encdec(assembly("fence rw,io")));
- /*PC = __GetSlice_int(64, elf_entry(), 0);
+ PC = __GetSlice_int(64, elf_entry(), 0);
try {
init_sys ();
loop ()
} catch {
Error_not_implemented(s) => print_string("Error: Not implemented: ", s),
Error_internal_error() => print("Error: internal error")
- }*/
+ }
}