diff options
| author | Prashanth Mundkur | 2018-05-07 17:37:02 -0700 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-05-07 17:37:02 -0700 |
| commit | 5322e93e4bf762a1c2bc111956462dcf64cd1083 (patch) | |
| tree | 8d5ebed0a1db87861204659e7426586533af6f8d /riscv | |
| parent | 20a27cec5e74027b79e1d28bc885d9ca8af3474d (diff) | |
Log trap value on traps.
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/riscv_sys.sail | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/riscv_sys.sail b/riscv/riscv_sys.sail index ce5ef321..6e5a8844 100644 --- a/riscv/riscv_sys.sail +++ b/riscv/riscv_sys.sail @@ -619,7 +619,7 @@ union ctl_result = { function handle_trap(del_priv : Privilege, intr : bool, c : exc_code, pc : xlenbits, info : option(xlenbits)) -> xlenbits = { - print("handling " ^ (if intr then "int#" else "exc#") ^ BitStr(c) ^ " at priv " ^ del_priv); + print("handling " ^ (if intr then "int#" else "exc#") ^ BitStr(c) ^ " at priv " ^ del_priv ^ " with tval " ^ BitStr(tval(info))); match (del_priv) { Machine => { mcause->IsInterrupt() = intr; |
