diff options
| author | Prashanth Mundkur | 2018-06-08 14:52:49 -0700 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-06-08 14:52:49 -0700 |
| commit | 4d0eee64305705239b40c7b3328d45180a60f964 (patch) | |
| tree | d83aecee542d4fab101cc62c8e94862b18beeccd /riscv | |
| parent | e9c0f8403a8c4b55aeed2173740f11714edf4c8b (diff) | |
Make the simulation loop use the platform interface to detect exits via htif.
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/platform.ml | 4 | ||||
| -rw-r--r-- | riscv/riscv_step.sail | 11 |
2 files changed, 8 insertions, 7 deletions
diff --git a/riscv/platform.ml b/riscv/platform.ml index 15b28abb..8d93ad4a 100644 --- a/riscv/platform.ml +++ b/riscv/platform.ml @@ -92,6 +92,10 @@ let term_read () = (* returns starting value for PC, i.e. start of reset vector *) let init elf_file = Elf.load_elf elf_file; + + Printf.printf "\nRegistered htif_tohost at 0x%Lx.\n" (Big_int.to_int64 (Elf.elf_tohost ())); + Printf.printf "Registered clint at 0x%Lx (size 0x%Lx).\n%!" P.clint_base P.clint_size; + let start_pc = Elf.Big_int.to_int64 (Elf.elf_entry ()) in let rom = make_rom start_pc in let rom_base = Big_int.of_int64 P.rom_base in diff --git a/riscv/riscv_step.sail b/riscv/riscv_step.sail index d241b84a..93060f68 100644 --- a/riscv/riscv_step.sail +++ b/riscv/riscv_step.sail @@ -103,13 +103,10 @@ function loop (tohost_addr) = { if retired then i = i + 1; /* check htif exit */ - let tohost_val = __ReadRAM(64, 4, 0x0000_0000_0000_0000, tohost); - if unsigned(tohost_val) != 0 then { - let exit_val = unsigned(tohost_val >> 0b1) in - if exit_val == 0 then - print("SUCCESS") - else - print_int("FAILURE: ", exit_val); + if htif_done then { + let exit_val = unsigned(htif_exit_code); + if exit_val == 0 then print("SUCCESS") + else print_int("FAILURE: ", exit_val); exit(()); } } |
