summaryrefslogtreecommitdiff
path: root/riscv
diff options
context:
space:
mode:
authorJon French2018-07-10 15:00:25 +0100
committerJon French2018-07-10 15:01:00 +0100
commit472097b3fb486d474a427427c1c38298a2ee1fc3 (patch)
tree1a416ec935e6070ed8d99fc92fbca4ff55030698 /riscv
parent5c699daef37feb8ae0d22548d9771ea0f50b49a0 (diff)
disable printing when compiling to Lem to keep rmem happy
Diffstat (limited to 'riscv')
-rw-r--r--riscv/riscv_extras.lem4
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/riscv_extras.lem b/riscv/riscv_extras.lem
index 88ac3e6f..60b635da 100644
--- a/riscv/riscv_extras.lem
+++ b/riscv/riscv_extras.lem
@@ -106,7 +106,7 @@ val shift_bits_left : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvecto
let shift_bits_left v m = shiftl v (uint m)
val print_string : string -> string -> unit
-let print_string msg s = print_endline (msg ^ s)
+let print_string msg s = () (* print_endline (msg ^ s) *)
val prerr_string : string -> string -> unit
let prerr_string msg s = prerr_endline (msg ^ s)
@@ -115,4 +115,4 @@ val prerr_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit
let prerr_bits msg bs = prerr_endline (msg ^ (show_bitlist (bits_of bs)))
val print_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit
-let print_bits msg bs = print_endline (msg ^ (show_bitlist (bits_of bs)))
+let print_bits msg bs = () (* print_endline (msg ^ (show_bitlist (bits_of bs))) *)