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authorJon French2018-05-10 11:30:45 +0100
committerJon French2018-05-10 11:30:45 +0100
commit43a6832d12fab718b502d82545301d7e766745c5 (patch)
tree498c1dd4faa1525feb2f12c086631c5a011a4590 /riscv
parenta67ad9ca27c5e2909c852a61f34b18a3414efc46 (diff)
refining spaces mappings
Diffstat (limited to 'riscv')
-rw-r--r--riscv/riscv.sail6
1 files changed, 3 insertions, 3 deletions
diff --git a/riscv/riscv.sail b/riscv/riscv.sail
index d8641a06..a40ec53f 100644
--- a/riscv/riscv.sail
+++ b/riscv/riscv.sail
@@ -180,12 +180,12 @@ mapping reg_name = {
val operand_sep : unit <-> string
mapping operand_sep = {
- () <-> opt_spaces(0) ^^ "," ^^ opt_spaces(1)
+ () <-> opt_spaces() ^^ "," ^^ def_spaces()
}
-val itype_operands : (bits(20), regbits, regbits) <-> string
+val itype_operands : (bits(12), regbits, regbits) <-> string
mapping itype_operands = {
- (imm, rs1, rd) <-> spaces(1) ^^ reg_name(rd) ^^ operand_sep() ^^ reg_name(rs1) ^^ operand_sep() ^^ hex_bits(20, imm)
+ (imm, rs1, rd) <-> spaces() ^^ reg_name(rd) ^^ operand_sep() ^^ reg_name(rs1) ^^ operand_sep() ^^ hex_bits(12, imm)
}
mapping clause assembly = ITYPE(imm, rs1, rd, RISCV_ADDI) <-> "addi" ^^ itype_operands(imm, rs1, rd)