diff options
| author | Alasdair Armstrong | 2018-02-06 13:53:13 +0000 |
|---|---|---|
| committer | Alasdair Armstrong | 2018-02-06 13:53:13 +0000 |
| commit | 38a4fd1354546882ba9d0edbd811995220c53c57 (patch) | |
| tree | 925456e3fb03895d9824f2f8c985e4cf5502ddd4 /riscv | |
| parent | 67639c2c387a014b3855b4d816c82805d3e5fa12 (diff) | |
Make small change to improve readability of riscv duopod
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/riscv_duopod.sail | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/riscv_duopod.sail b/riscv/riscv_duopod.sail index e0eaf949..2c303432 100644 --- a/riscv/riscv_duopod.sail +++ b/riscv/riscv_duopod.sail @@ -6,7 +6,7 @@ type regno ('n : Int), 0 <= 'n < 32 = atom('n) type regbits = bits(5) val cast regbits_to_regno : bits(5) -> {'n, 0 <= 'n < 32. regno('n)} -function regbits_to_regno b = let 'r = unsigned(b) in r +function regbits_to_regno b = let r as atom(_) = unsigned(b) in r /* Architectural state */ |