diff options
| author | Robert Norton | 2018-01-29 10:34:14 +0000 |
|---|---|---|
| committer | Robert Norton | 2018-01-29 12:03:16 +0000 |
| commit | 36c37fc31421f4965a3613ae9a257cc23ac623cd (patch) | |
| tree | 81e613585d737f3c0fbaeeaa5880907d4c60fb83 /riscv | |
| parent | d9d064c0d91cc072e300f6ca7b6c12ca640c7712 (diff) | |
Fix error in RISCV: SLLI and SRLI were swapped...
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/riscv.sail | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/riscv/riscv.sail b/riscv/riscv.sail index beb29327..c19e84e6 100644 --- a/riscv/riscv.sail +++ b/riscv/riscv.sail @@ -104,8 +104,8 @@ function clause decode 0b010000 @ shamt : bits(6) @ rs1 : regbits @ 0b101 @ rd : function clause execute (SHIFTIOP(shamt, rs1, rd, op)) = let rs1_val = rGPR(rs1) in let result : bits(64) = match op { - RISCV_SLLI => rs1_val >> shamt, - RISCV_SRLI => rs1_val << shamt, + RISCV_SLLI => rs1_val << shamt, + RISCV_SRLI => rs1_val >> shamt, RISCV_SRAI => shift_right_arith64(rs1_val, shamt) } in wGPR(rd, result) @@ -220,8 +220,8 @@ function clause decode 0b0100000 @ shamt : bits(5) @ rs1 : regbits @ 0b101 @ rd function clause execute (SHIFTW(shamt, rs1, rd, op)) = let rs1_val = (rGPR(rs1))[31..0] in let result : bits(32) = match op { - RISCV_SLLI => rs1_val >> shamt, - RISCV_SRLI => rs1_val << shamt, + RISCV_SLLI => rs1_val << shamt, + RISCV_SRLI => rs1_val >> shamt, RISCV_SRAI => shift_right_arith32(rs1_val, shamt) } in wGPR(rd, EXTS(result)) |
