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authorJon French2018-05-10 13:13:56 +0100
committerJon French2018-05-10 13:13:56 +0100
commit2fd802b56d098f547420621b92e7372ec7f55842 (patch)
tree0512450e8f0acafc9da8086d6614511bacfc59ef /riscv
parentb7307bd33a1c0fe7190fc4b34a9d3eca9beda565 (diff)
move common mappings to riscv_types.sail
Diffstat (limited to 'riscv')
-rw-r--r--riscv/riscv.sail44
-rw-r--r--riscv/riscv_types.sail43
2 files changed, 43 insertions, 44 deletions
diff --git a/riscv/riscv.sail b/riscv/riscv.sail
index 8e734576..e80604ac 100644
--- a/riscv/riscv.sail
+++ b/riscv/riscv.sail
@@ -139,50 +139,6 @@ function clause print_insn (ITYPE(imm, rs1, rd, op)) =
insn ^ rd ^ ", " ^ rs1 ^ ", " ^ BitStr(imm)
-
-
-
-val reg_name : bits(5) <-> string
-mapping reg_name = {
- 0b00000 <-> "zero",
- 0b00001 <-> "ra",
- 0b00010 <-> "sp",
- 0b00011 <-> "gp",
- 0b00100 <-> "tp",
- 0b00101 <-> "t0",
- 0b00110 <-> "t1",
- 0b00111 <-> "t2",
- 0b01000 <-> "fp",
- 0b01001 <-> "s1",
- 0b01010 <-> "a0",
- 0b01011 <-> "a1",
- 0b01100 <-> "a2",
- 0b01101 <-> "a3",
- 0b01110 <-> "a4",
- 0b01111 <-> "a5",
- 0b10000 <-> "a6",
- 0b10001 <-> "a7",
- 0b10010 <-> "s2",
- 0b10011 <-> "s3",
- 0b10100 <-> "s4",
- 0b10101 <-> "s5",
- 0b10110 <-> "s6",
- 0b10111 <-> "s7",
- 0b11000 <-> "s8",
- 0b11001 <-> "s9",
- 0b11010 <-> "s10",
- 0b11011 <-> "s11",
- 0b11100 <-> "t3",
- 0b11101 <-> "t4",
- 0b11110 <-> "t5",
- 0b11111 <-> "t6"
-}
-
-val operand_sep : unit <-> string
-mapping operand_sep = {
- () <-> opt_spaces() ^^ "," ^^ def_spaces()
-}
-
val itype_operands : (bits(12), regbits, regbits) <-> string
mapping itype_operands = {
(imm, rs1, rd) <-> spaces() ^^ reg_name(rd) ^^ operand_sep() ^^ reg_name(rs1) ^^ operand_sep() ^^ hex_bits_12(imm)
diff --git a/riscv/riscv_types.sail b/riscv/riscv_types.sail
index ee0eb94d..8eefd9d6 100644
--- a/riscv/riscv_types.sail
+++ b/riscv/riscv_types.sail
@@ -323,3 +323,46 @@ enum ropw = {RISCV_ADDW, RISCV_SUBW, RISCV_SLLW, RISCV_SRLW, RISCV_SRAW} /* reg-
enum amoop = {AMOSWAP, AMOADD, AMOXOR, AMOAND, AMOOR, AMOMIN, AMOMAX, AMOMINU, AMOMAXU} /* AMO ops */
enum csrop = {CSRRW, CSRRS, CSRRC}
enum word_width = {BYTE, HALF, WORD, DOUBLE}
+
+/* mappings for assembly */
+
+val reg_name : bits(5) <-> string
+mapping reg_name = {
+ 0b00000 <-> "zero",
+ 0b00001 <-> "ra",
+ 0b00010 <-> "sp",
+ 0b00011 <-> "gp",
+ 0b00100 <-> "tp",
+ 0b00101 <-> "t0",
+ 0b00110 <-> "t1",
+ 0b00111 <-> "t2",
+ 0b01000 <-> "fp",
+ 0b01001 <-> "s1",
+ 0b01010 <-> "a0",
+ 0b01011 <-> "a1",
+ 0b01100 <-> "a2",
+ 0b01101 <-> "a3",
+ 0b01110 <-> "a4",
+ 0b01111 <-> "a5",
+ 0b10000 <-> "a6",
+ 0b10001 <-> "a7",
+ 0b10010 <-> "s2",
+ 0b10011 <-> "s3",
+ 0b10100 <-> "s4",
+ 0b10101 <-> "s5",
+ 0b10110 <-> "s6",
+ 0b10111 <-> "s7",
+ 0b11000 <-> "s8",
+ 0b11001 <-> "s9",
+ 0b11010 <-> "s10",
+ 0b11011 <-> "s11",
+ 0b11100 <-> "t3",
+ 0b11101 <-> "t4",
+ 0b11110 <-> "t5",
+ 0b11111 <-> "t6"
+}
+
+val operand_sep : unit <-> string
+mapping operand_sep = {
+ () <-> opt_spaces() ^^ "," ^^ def_spaces()
+}