diff options
| author | Prashanth Mundkur | 2018-07-09 00:15:20 -0700 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-07-09 00:15:20 -0700 |
| commit | 2c1dfb042ecc10c0ca7868ab186ff8235926d8d3 (patch) | |
| tree | a98714104f35ba1037c12e59ba93cdb69b2fc7f4 /riscv | |
| parent | b9d6151e8671a03eb58f2065e85367fff0a27cf0 (diff) | |
Support writes to misa.C in riscv.
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/riscv.sail | 4 | ||||
| -rw-r--r-- | riscv/riscv_sys.sail | 18 |
2 files changed, 15 insertions, 7 deletions
diff --git a/riscv/riscv.sail b/riscv/riscv.sail index 0b651f04..7ba02a77 100644 --- a/riscv/riscv.sail +++ b/riscv/riscv.sail @@ -1159,7 +1159,7 @@ function readCSR csr : csreg -> xlenbits = 0x305 => mtvec.bits(), 0x306 => EXTZ(mcounteren.bits()), 0x340 => mscratch, - 0x341 => mepc, + 0x341 => mepc & pc_alignment_mask(), 0x342 => mcause.bits(), 0x343 => mtval, 0x344 => mip.bits(), @@ -1175,7 +1175,7 @@ function readCSR csr : csreg -> xlenbits = 0x105 => stvec.bits(), 0x106 => EXTZ(scounteren.bits()), 0x140 => sscratch, - 0x141 => sepc, + 0x141 => sepc & pc_alignment_mask(), 0x142 => scause.bits(), 0x143 => stval, 0x144 => lower_mip(mip, mideleg).bits(), diff --git a/riscv/riscv_sys.sail b/riscv/riscv_sys.sail index 3152b95c..36942eed 100644 --- a/riscv/riscv_sys.sail +++ b/riscv/riscv_sys.sail @@ -40,9 +40,14 @@ bitfield Misa : bits(64) = { } register misa : Misa -function legalize_misa(m : Misa, v : xlenbits) -> Misa = - /* Ignore all writes for now. */ - m +function legalize_misa(m : Misa, v : xlenbits) -> Misa = { + /* Allow modifications to C. */ + let v = Mk_Misa(v); + // Suppress changing C if nextPC would become misaligned. + if v.C() == false & nextPC[1] == true + then m + else update_C(m, v.C()) +} bitfield Mstatus : bits(64) = { SD : 63, @@ -112,6 +117,9 @@ function haveRVC() -> bool = { misa.C() == true } function haveMulDiv() -> bool = { misa.M() == true } function haveFP() -> bool = { misa.F() == true | misa.D() == true } +function pc_alignment_mask() -> xlenbits = + ~(EXTZ(if misa.C() == true then 0b00 else 0b10)) + /* interrupt registers */ bitfield Minterrupts : bits(64) = { @@ -866,7 +874,7 @@ function handle_exception(cur_priv : Privilege, ctl : ctl_result, print("ret-ing from " ^ prev_priv ^ " to " ^ cur_privilege); cancel_reservation(); - mepc + mepc & pc_alignment_mask() }, (_, CTL_SRET()) => { let prev_priv = cur_privilege; @@ -879,7 +887,7 @@ function handle_exception(cur_priv : Privilege, ctl : ctl_result, print("ret-ing from " ^ prev_priv ^ " to " ^ cur_privilege); cancel_reservation(); - sepc + sepc & pc_alignment_mask() } } } |
