diff options
| author | Prashanth Mundkur | 2018-05-07 17:10:25 -0700 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-05-07 17:10:25 -0700 |
| commit | 20a27cec5e74027b79e1d28bc885d9ca8af3474d (patch) | |
| tree | 7f5e9dcd911963c020d81c1c1afac134b49dad3e /riscv | |
| parent | d541425ae8f63e8a9b375877b825cc3d91b9b9d5 (diff) | |
Fix a missed csr read.
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/riscv.sail | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/riscv.sail b/riscv/riscv.sail index 1b5a632c..fb8d1c08 100644 --- a/riscv/riscv.sail +++ b/riscv/riscv.sail @@ -823,6 +823,7 @@ function readCSR csr : csreg -> xlenbits = 0xF13 => mimpid, 0xF14 => mhartid, 0x300 => mstatus.bits(), + 0x301 => misa.bits(), 0x302 => medeleg.bits(), 0x303 => mideleg.bits(), 0x304 => mie.bits(), |