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| author | Brian Campbell | 2018-08-13 16:25:18 +0100 |
|---|---|---|
| committer | Brian Campbell | 2018-08-13 16:25:18 +0100 |
| commit | 1f3253c106e40cbfe6ecd79b281b45abf708663b (patch) | |
| tree | 386aba5a5f3e778571883d40ca45c12458c4175a /riscv | |
| parent | 0fc1d90ebc7b6bda46e593893dc92acad896ae90 (diff) | |
Add constraints to RISC-V duopod, makefile rules
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/Makefile | 4 | ||||
| -rw-r--r-- | riscv/riscv_duopod.sail | 4 |
2 files changed, 6 insertions, 2 deletions
diff --git a/riscv/Makefile b/riscv/Makefile index 5093c41e..6499fe7d 100644 --- a/riscv/Makefile +++ b/riscv/Makefile @@ -81,9 +81,12 @@ COQ_LIBS = -R ../../bbv/theories bbv -R ../lib/coq Sail riscv.v riscv_types.v: $(SAIL_SRCS) $(SAIL) $(SAIL_FLAGS) -dcoq_undef_axioms -coq -o riscv -coq_lib riscv_extras $(SAIL_SRCS) +riscv_duopod.v riscv_duopod_types.v: prelude.sail riscv_duopod.sail + $(SAIL) $(SAIL_FLAGS) -dcoq_undef_axioms -coq -o riscv_duopod -coq_lib riscv_extras $^ %.vo: %.v coqc $(COQ_LIBS) $< riscv.vo: riscv_types.vo riscv_extras.vo +riscv_duopod.vo: riscv_duopod_types.vo riscv_extras.vo # we exclude prelude.sail here, most code there should move to sail lib LOC_FILES:=$(SAIL_SRCS) main.sail @@ -98,5 +101,6 @@ clean: -rm -f riscvScript.sml riscv_typesScript.sml riscv_extrasScript.sml -rm -f platform_main.native platform coverage.native -rm -f riscv.vo riscv_types.vo riscv_extras.vo riscv.v riscv_types.v + -rm -f riscv_duopod.vo riscv_duopod_types.vo riscv_duopod.v riscv_duopod_types.v -Holmake cleanAll ocamlbuild -clean diff --git a/riscv/riscv_duopod.sail b/riscv/riscv_duopod.sail index ff1e4065..0a5a7f8c 100644 --- a/riscv/riscv_duopod.sail +++ b/riscv/riscv_duopod.sail @@ -5,7 +5,7 @@ type xlen_t = bits(64) type regno ('n : Int), 0 <= 'n < 32 = atom('n) type regbits = bits(5) -val zeros : forall 'n. atom('n) -> bits('n) +val zeros : forall 'n, 'n >= 0. atom('n) -> bits('n) function zeros n = replicate_bits(0b0, n) val cast regbits_to_regno : bits(5) -> {'n, 0 <= 'n < 32. regno('n)} @@ -35,7 +35,7 @@ overload X = {rX, wX} /* Accessors for memory */ -val MEMr : forall 'n. (xlen_t, atom('n)) -> bits(8 * 'n) effect {rmem} +val MEMr : forall 'n, 'n >= 0. (xlen_t, atom('n)) -> bits(8 * 'n) effect {rmem} function MEMr (addr, width) = match __RISCV_read(addr, width, false, false, false) { Some(v) => v, None() => zeros(8 * width) } |