diff options
| author | Prashanth Mundkur | 2018-04-11 16:09:31 -0700 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-04-11 18:13:58 -0700 |
| commit | 1c16429e62e853b2460eb12d578c2758a3be0f75 (patch) | |
| tree | f1d9b5e3a84d1c5ac2cc08276682c956ed951a06 /riscv | |
| parent | 67cfa80cc0c10780ff7d86b69e2311c4e8f621d0 (diff) | |
Add some misc informational m-mode registers that are used in a test.
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/riscv.sail | 4 | ||||
| -rw-r--r-- | riscv/riscv_sys.sail | 10 |
2 files changed, 11 insertions, 3 deletions
diff --git a/riscv/riscv.sail b/riscv/riscv.sail index 34fc53fe..1471f504 100644 --- a/riscv/riscv.sail +++ b/riscv/riscv.sail @@ -529,6 +529,10 @@ function isCSRImplemented csr : bits(12) -> bool = function readCSR csr: bits(12) -> xlenbits = match csr { + 0xF11 => mvendorid, + 0xF12 => marchid, + 0xF13 => mimpid, + 0xF14 => mhartid, 0x300 => mstatus.bits(), 0x302 => medeleg.bits(), 0x303 => mideleg.bits(), diff --git a/riscv/riscv_sys.sail b/riscv/riscv_sys.sail index 1786766f..43deacb0 100644 --- a/riscv/riscv_sys.sail +++ b/riscv/riscv_sys.sail @@ -132,12 +132,16 @@ register mepc : xlenbits register mtval : xlenbits register mscratch : xlenbits -/* other registers */ +/* informational registers */ +register mvendorid : xlenbits +register mimpid : xlenbits +register marchid : xlenbits +/* TODO: this should be readonly, and always 0 for now */ +register mhartid : xlenbits +/* physical memory protection configuration */ register pmpaddr0 : xlenbits register pmpcfg0 : xlenbits -/* TODO: this should be readonly, and always 0 for now */ -register mhartid : xlenbits /* instruction control flow */ |