diff options
| author | Shaked Flur | 2018-07-12 08:44:42 +0100 |
|---|---|---|
| committer | Shaked Flur | 2018-07-12 08:44:42 +0100 |
| commit | 0b7273789c94cc1de640158d4bb3a6ac4e0e7a25 (patch) | |
| tree | 6f9f28b523047b78995c499f1518e53f53fc4fe9 /riscv | |
| parent | 8d95266216f3249e40c01977065600a4363ea42e (diff) | |
Fixed a nested comment issue
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/riscv.sail | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/riscv.sail b/riscv/riscv.sail index 548091e2..497c5e7a 100644 --- a/riscv/riscv.sail +++ b/riscv/riscv.sail @@ -90,7 +90,7 @@ function clause execute (RISCV_JALR(imm, rs1, rd)) = { some manner, but for now, we just reorder the previous two lines to improve simulator performance in the sequential model, as below: let newPC : xlenbits = X(rs1) + EXTS(imm); - X(rd) = nextPC; /* compatible with JALR, C.JR and C.JALR + X(rd) = nextPC; /* compatible with JALR, C.JR and C.JALR */ */ nextPC = newPC[63..1] @ 0b0; true |
