Add some missing rv64i instructions, discovered when annotating the riscv isa spec.

2 files changed, 29 insertions, 0 deletions

diff --git a/riscv/riscv.sail b/riscv/riscv.sail
index f81de3e9..d9baf299 100644
--- a/riscv/riscv.sail
+++ b/riscv/riscv.sail
@@ -460,6 +460,33 @@ mapping clause assembly = RTYPEW(rs2, rs1, rd, op)
                       <-> rtypew_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)
 
 /* ****************************************************************** */
+union clause ast = SHIFTIWOP : (bits(5), regbits, regbits, sopw)
+
+mapping clause encdec = SHIFTIWOP(shamt, rs1, rd, RISCV_SLLIW) <-> 0b0000000 @ shamt @ rs1 @ 0b001 @ rd @ 0b0011011
+mapping clause encdec = SHIFTIWOP(shamt, rs1, rd, RISCV_SRLIW) <-> 0b0000000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0011011
+mapping clause encdec = SHIFTIWOP(shamt, rs1, rd, RISCV_SRAIW) <-> 0b0100000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0011011
+
+function clause execute (SHIFTIWOP(shamt, rs1, rd, op)) = {
+  let rs1_val = X(rs1);
+  let result : xlenbits = match op {
+    RISCV_SLLIW => EXTS(rs1_val[31..0] << shamt),
+    RISCV_SRLIW => EXTS(rs1_val[31..0] >> shamt),
+    RISCV_SRAIW => EXTS(shift_right_arith32(rs1_val[31..0], shamt))
+  };
+  X(rd) = result;
+  true
+}
+
+mapping shiftiwop_mnemonic : sopw <-> string = {
+  RISCV_SLLIW <-> "slliw",
+  RISCV_SRLIW <-> "srliw",
+  RISCV_SRAIW <-> "sraiw"
+}
+
+mapping clause assembly = SHIFTIWOP(shamt, rs1, rd, op)
+                      <-> shiftiwop_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ hex_bits_5(shamt)
+
+/* ****************************************************************** */
 /* FIXME: separate these out into separate ast variants */
 union clause ast = MUL : (regbits, regbits, regbits, bool, bool, bool)
 
diff --git a/riscv/riscv_types.sail b/riscv/riscv_types.sail
index 77df74db..9a95ced9 100644
--- a/riscv/riscv_types.sail
+++ b/riscv/riscv_types.sail
@@ -450,6 +450,8 @@ enum rop = {RISCV_ADD, RISCV_SUB, RISCV_SLL, RISCV_SLT,
 
 enum ropw  = {RISCV_ADDW, RISCV_SUBW, RISCV_SLLW,
               RISCV_SRLW, RISCV_SRAW}             /* reg-reg 32-bit ops */
+enum sopw = {RISCV_SLLIW, RISCV_SRLIW,
+             RISCV_SRAIW}                         /* RV64-only shift ops */
 enum amoop = {AMOSWAP, AMOADD, AMOXOR, AMOAND, AMOOR,
               AMOMIN, AMOMAX, AMOMINU, AMOMAXU}   /* AMO ops */
 enum csrop = {CSRRW, CSRRS, CSRRC}                /* CSR ops */