diff options
| author | Prashanth Mundkur | 2018-06-25 14:39:30 -0700 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-06-25 15:36:08 -0700 |
| commit | 07d0c0c72c0430a69552edcfb64d7640774c262b (patch) | |
| tree | 3b3d416927dd088fc7817f22be85ffd938974032 /riscv | |
| parent | c091410169c5ead5c39fa72d80fb52e22cd0d3dd (diff) | |
Hook in the missed misa legalizer.
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/riscv.sail | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/riscv.sail b/riscv/riscv.sail index 2d3441d7..aad6c731 100644 --- a/riscv/riscv.sail +++ b/riscv/riscv.sail @@ -1134,6 +1134,7 @@ function writeCSR (csr : csreg, value : xlenbits) -> unit = match csr { /* machine mode */ 0x300 => { mstatus = legalize_mstatus(mstatus, value); Some(mstatus.bits()) }, + 0x301 => { misa = legalize_misa(misa, value); Some(misa.bits()) }, 0x302 => { medeleg = legalize_medeleg(medeleg, value); Some(medeleg.bits()) }, 0x303 => { mideleg = legalize_mideleg(mideleg, value); Some(mideleg.bits()) }, 0x304 => { mie = legalize_mie(mie, value); Some(mie.bits()) }, |