RISC-V: allow platform ram size to be configurable.

4 files changed, 37 insertions, 13 deletions

diff --git a/riscv/platform.ml b/riscv/platform.ml
index 06486ca2..f2e9f7b6 100644
--- a/riscv/platform.ml
+++ b/riscv/platform.ml
@@ -69,7 +69,7 @@ let bits_of_int64 i =
 let rom_size_ref = ref 0
 let make_rom start_pc =
   let reset_vec = List.concat (List.map P.uint32_to_bytes (P.reset_vec_int start_pc)) in
-  let dtb = P.make_dtb P.dts in
+  let dtb = P.make_dtb (P.make_dts ()) in
   let rom = reset_vec @ dtb in
   ( rom_size_ref := List.length rom;
     (*
@@ -89,7 +89,7 @@ let rom_base () = bits_of_int64 P.rom_base
 let rom_size () = bits_of_int   !rom_size_ref
 
 let dram_base () = bits_of_int64 P.dram_base
-let dram_size () = bits_of_int64 P.dram_size
+let dram_size () = bits_of_int64 !P.dram_size_ref
 
 let htif_tohost () =
   bits_of_int64 (Big_int.to_int64 (Elf.elf_tohost ()))
diff --git a/riscv/platform_impl.ml b/riscv/platform_impl.ml
index c5cc3fff..3eb82179 100644
--- a/riscv/platform_impl.ml
+++ b/riscv/platform_impl.ml
@@ -41,11 +41,12 @@ let reset_vec_int start_pc = [
 (* address map *)
 
 let dram_base  = 0x80000000L;;  (* Spike::DRAM_BASE *)
-let dram_size  = Int64.(shift_left 2048L 20)
 let clint_base = 0x02000000L;;  (* Spike::CLINT_BASE *)
 let clint_size = 0x000c0000L;;  (* Spike::CLINT_SIZE *)
 let rom_base   = 0x00001000L;;  (* Spike::DEFAULT_RSTVEC *)
 
+let dram_size_ref = ref (Int64.(shift_left 2048L 20))
+
 type mem_region = {
     addr : Int64.t;
     size : Int64.t
@@ -106,9 +107,10 @@ let spike_dts isa_spec cpu_hz insns_per_rtc_tick mems =
 let cpu_hz = 1000000000;;
 let insns_per_tick = 100;;
 
-let mems = [ { addr = dram_base;
-               size = dram_size } ];;
-let dts = spike_dts "rv64imac" cpu_hz insns_per_tick mems;;
+let make_mems () = [{ addr = dram_base;
+                      size = !dram_size_ref }];;
+
+let make_dts () = spike_dts "rv64imac" cpu_hz insns_per_tick (make_mems ());;
 
 let bytes_to_string bytes =
   String.init (List.length bytes) (fun i -> Char.chr (List.nth bytes i))
@@ -125,6 +127,9 @@ let set_dtc path =
     ( Printf.eprintf "Error accessing %s: %s\n%!" path (Unix.error_message e);
       exit 1)
 
+let set_dram_size mb =
+  dram_size_ref := Int64.(shift_left (Int64.of_int mb) 20)
+
 let make_dtb dts = (* Call the dtc compiler, assumed to be at /usr/bin/dtc *)
   try
     let cmd = Printf.sprintf "%s -I dts" !dtc_path in
@@ -172,8 +177,8 @@ let rec term_read () =
 let show_bytes s =
   output_string stdout s
 
-let dump_dts () = show_bytes dts
-let dump_dtb () = show_bytes (bytes_to_string (make_dtb dts))
+let dump_dts () = show_bytes (make_dts ())
+let dump_dtb () = show_bytes (bytes_to_string (make_dtb (make_dts ())))
 
 (*
 let save_string_to_file s fname =
diff --git a/riscv/platform_main.ml b/riscv/platform_main.ml
index b33247f1..1c9ba209 100644
--- a/riscv/platform_main.ml
+++ b/riscv/platform_main.ml
@@ -76,6 +76,9 @@ let options = Arg.align ([("-dump-dts",
                           ("-mtval-has-illegal-inst-bits",
                            Arg.Set P.config_mtval_has_illegal_inst_bits,
                            " mtval stores instruction bits on an illegal instruction exception");
+                          ("-ram-size",
+                           Arg.Int PI.set_dram_size,
+                           " size of physical ram memory to use (in MB)");
                           ("-with-dtc",
                            Arg.String PI.set_dtc,
                            " full path to dtc to use")
diff --git a/riscv/riscv_sim.c b/riscv/riscv_sim.c
index 06f9bd66..394277a7 100644
--- a/riscv/riscv_sim.c
+++ b/riscv/riscv_sim.c
@@ -52,6 +52,7 @@ size_t spike_dtb_len = 0;
 static struct option options[] = {
   {"enable-dirty",                no_argument,       0, 'd'},
   {"enable-misaligned",           no_argument,       0, 'm'},
+  {"ram-size",                    required_argument, 0, 'z'},
   {"mtval-has-illegal-inst-bits", no_argument,       0, 'i'},
   {"dump-dts",                    no_argument,       0, 's'},
   {"device-tree-blob",            required_argument, 0, 'b'},
@@ -75,7 +76,7 @@ static void dump_dts(void)
 {
 #ifdef SPIKE
   size_t dts_len = 0;
-  struct tv_spike_t *s = tv_init("RV64IMAC", 0);
+  struct tv_spike_t *s = tv_init("RV64IMAC", rv_ram_size, 0);
   tv_get_dts(s, NULL, &dts_len);
   if (dts_len > 0) {
     unsigned char *dts = (unsigned char *)malloc(dts_len + 1);
@@ -122,14 +123,17 @@ static void read_dtb(const char *path)
 char *process_args(int argc, char **argv)
 {
   int c, idx = 1;
+  uint64_t ram_size = 0;
   while(true) {
-    c = getopt_long(argc, argv, "dmsb:t:v:h", options, &idx);
+    c = getopt_long(argc, argv, "dmsz:b:t:v:h", options, &idx);
     if (c == -1) break;
     switch (c) {
     case 'd':
+      fprintf(stderr, "enabling dirty update.\n");
       rv_enable_dirty_update = true;
       break;
     case 'm':
+      fprintf(stderr, "enabling misaligned access.\n");
       rv_enable_misaligned = true;
       break;
     case 'i':
@@ -137,6 +141,13 @@ char *process_args(int argc, char **argv)
     case 's':
       do_dump_dts = true;
       break;
+    case 'z':
+      ram_size = atol(optarg);
+      if (ram_size) {
+        fprintf(stderr, "setting ram-size to %ld MB\n", ram_size);
+        rv_ram_size = ram_size << 20;
+      }
+      break;
     case 'b':
       dtb_file = strdup(optarg);
       break;
@@ -179,11 +190,11 @@ uint64_t load_sail(char *f)
   return entry;
 }
 
-void init_spike(const char *f, uint64_t entry)
+void init_spike(const char *f, uint64_t entry, uint64_t ram_size)
 {
 #ifdef SPIKE
   bool mismatch = false;
-  s = tv_init("RV64IMAC", 1);
+  s = tv_init("RV64IMAC", ram_size, 1);
   if (tv_is_dirty_enabled(s) != rv_enable_dirty_update) {
     mismatch = true;
     fprintf(stderr, "inconsistent enable-dirty-update setting: spike %s, sail %s\n",
@@ -196,6 +207,11 @@ void init_spike(const char *f, uint64_t entry)
             tv_is_misaligned_enabled(s) ? "on" : "off",
             rv_enable_misaligned        ? "on" : "off");
   }
+  if (tv_ram_size(s) != rv_ram_size) {
+    mismatch = true;
+    fprintf(stderr, "inconsistent ram-size setting: spike %lx, sail %lx\n",
+            tv_ram_size(s), rv_ram_size);
+  }
   if (mismatch) exit(1);
 
   /* The initialization order below matters. */
@@ -491,7 +507,7 @@ int main(int argc, char **argv)
   /* initialize spike before sail so that we can access the device-tree blob,
    * until we roll our own.
    */
-  init_spike(file, entry);
+  init_spike(file, entry, rv_ram_size);
   init_sail(entry);
 
   if (!init_check(s)) finish(1);