diff options
| author | Prashanth Mundkur | 2018-06-09 17:25:34 -0700 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-06-09 19:27:24 -0700 |
| commit | ee44f49cf6180734ecfb749a8868b4f146a4bc41 (patch) | |
| tree | c672f396a70391512207081403a54f28fdf16a5d /riscv/riscv_sys.sail | |
| parent | 6b98912c895a72e436d0e3b6a72bd751ad29f156 (diff) | |
Some fixes to counteren handling.
Diffstat (limited to 'riscv/riscv_sys.sail')
| -rw-r--r-- | riscv/riscv_sys.sail | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/riscv/riscv_sys.sail b/riscv/riscv_sys.sail index fee13dee..b423b08f 100644 --- a/riscv/riscv_sys.sail +++ b/riscv/riscv_sys.sail @@ -571,7 +571,10 @@ function check_Counteren(csr : csreg, p : Privilege) -> bool = (0xC01, User) => scounteren.TM() == true, (0xC02, User) => scounteren.IR() == true, - (_, _) => true + (_, _) => /* no HPM counters for now */ + if 0xC03 <=_u csr & csr <=_u 0xC1F + then false + else true } function check_CSR(csr : csreg, p : Privilege, isWrite : bool) -> bool = @@ -782,7 +785,6 @@ function init_sys() -> unit = { mhartid = EXTZ(0b0); mcounteren->bits() = EXTZ(0b0); - scounteren->bits() = EXTZ(0b0); } function tick_clock() -> unit = { |