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authorPrashanth Mundkur2018-05-03 14:20:51 -0700
committerPrashanth Mundkur2018-05-03 14:21:06 -0700
commite39941e0ddf924502d17dc55f94fe09f1e4494d0 (patch)
tree32220d91298a293b481baeb81e428952b75b3991 /riscv/riscv_sys.sail
parent3f93ecbc6dbdc315b79de4ee69bf6bc6a6420d57 (diff)
Implement fetch to properly handle RVC and address translation, and add a step function for execution.
Diffstat (limited to 'riscv/riscv_sys.sail')
-rw-r--r--riscv/riscv_sys.sail5
1 files changed, 5 insertions, 0 deletions
diff --git a/riscv/riscv_sys.sail b/riscv/riscv_sys.sail
index e32836c7..e692e62d 100644
--- a/riscv/riscv_sys.sail
+++ b/riscv/riscv_sys.sail
@@ -687,6 +687,11 @@ function handle_mem_exception(addr : xlenbits, e : ExceptionType) -> unit = {
nextPC = handle_exception_ctl(cur_privilege, CTL_TRAP(t), PC)
}
+function handle_decode_exception(instbits : xlenbits) -> unit = {
+ let t : sync_exception = struct { trap = E_Illegal_Instr,
+ excinfo = Some(instbits) };
+ nextPC = handle_exception_ctl(cur_privilege, CTL_TRAP(t), PC)
+}
function init_sys() -> unit = {
cur_privilege = Machine;