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authorPrashanth Mundkur2018-04-20 17:35:48 -0700
committerPrashanth Mundkur2018-04-20 17:36:49 -0700
commit1b95665db9cf1deda3bfe243ed4038c47d1e940f (patch)
treeedc696c04df6634925d78fa0c18af6d29f3dc802 /riscv/riscv_sys.sail
parent8d74837e5b95866ed24795e81d1e685499067cfa (diff)
Add a riscv instruction printer for the execution log.
Diffstat (limited to 'riscv/riscv_sys.sail')
-rw-r--r--riscv/riscv_sys.sail66
1 files changed, 66 insertions, 0 deletions
diff --git a/riscv/riscv_sys.sail b/riscv/riscv_sys.sail
index 5551220f..ea80d640 100644
--- a/riscv/riscv_sys.sail
+++ b/riscv/riscv_sys.sail
@@ -399,6 +399,72 @@ register sepc : xlenbits
register scause : Mcause
register stval : xlenbits
+/* csr name printer */
+
+val cast csr_name : csreg -> string
+function csr_name(csr) = {
+ match (csr) {
+ /* user trap setup */
+ 0x000 => "ustatus",
+ 0x004 => "uie",
+ 0x005 => "utvec",
+ /* user floating-point context */
+ 0x001 => "fflags",
+ 0x002 => "frm",
+ 0x003 => "fcsr",
+ /* counter/timers */
+ 0xC00 => "cycle",
+ 0xC01 => "time",
+ 0xC02 => "instret",
+ 0xC80 => "cycleh",
+ 0xC81 => "timeh",
+ 0xC82 => "instreth",
+ /* TODO: other hpm counters */
+ /* supervisor trap setup */
+ 0x100 => "sstatus",
+ 0x102 => "sedeleg",
+ 0x103 => "sideleg",
+ 0x104 => "sie",
+ 0x105 => "stvec",
+ 0x106 => "scounteren",
+ /* supervisor trap handling */
+ 0x140 => "sscratch",
+ 0x141 => "sepc",
+ 0x142 => "scause",
+ 0x143 => "stval",
+ 0x144 => "sip",
+ /* supervisor protection and translation */
+ 0x180 => "satp",
+ /* machine information registers */
+ 0xF11 => "mvendorid",
+ 0xF12 => "marchid",
+ 0xF13 => "mimpid",
+ 0xF14 => "mhartid",
+ /* machine trap setup */
+ 0x300 => "mstatus",
+ 0x301 => "misa",
+ 0x302 => "medeleg",
+ 0x303 => "mideleg",
+ 0x304 => "mie",
+ 0x305 => "mtvec",
+ 0x306 => "mcounteren",
+ /* machine trap handling */
+ 0x340 => "mscratch",
+ 0x341 => "mepc",
+ 0x342 => "mcause",
+ 0x343 => "mtval",
+ 0x344 => "mip",
+ /* TODO: machine protection and translation */
+ /* machine counters/timers */
+ 0xB00 => "mcycle",
+ 0xB02 => "minstret",
+ 0xB80 => "mcycleh",
+ 0xB82 => "minstreth",
+ /* TODO: other hpm counters and events */
+ _ => "UNKNOWN"
+ }
+}
+
/* csr access control */
function csrAccess(csr : csreg) -> csrRW = csr[11..10]