Adapt checked_mem_read to have acquire/release/reserve arguments so

that this information propagates from the instruction definition to
the memory accesses. Necessary for Promising RISC-V concurrency model.

1 files changed, 2 insertions, 2 deletions

diff --git a/riscv/riscv_step.sail b/riscv/riscv_step.sail
index 8e5a0090..f9675115 100644
--- a/riscv/riscv_step.sail
+++ b/riscv/riscv_step.sail
@@ -21,7 +21,7 @@ function fetch() -> FetchResult =
        * well as to generate precise fault addresses in any fetch
        * exceptions.
        */
-      match checked_mem_read(Instruction, ppclo, 2) {
+      match checked_mem_read(Instruction, ppclo, 2, false, false, false) {
         MemException(e) => F_Error(E_Fetch_Access_Fault, PC),
         MemValue(ilo) => {
           if isRVC(ilo) then F_RVC(ilo)
@@ -30,7 +30,7 @@ function fetch() -> FetchResult =
             match translateAddr(PChi, Execute, Instruction) {
               TR_Failure(e) => F_Error(e, PChi),
               TR_Address(ppchi) => {
-                match checked_mem_read(Instruction, ppchi, 2) {
+                match checked_mem_read(Instruction, ppchi, 2, false, false, false) {
                   MemException(e) => F_Error(E_Fetch_Access_Fault, PChi),
                   MemValue(ihi) => F_Base(append(ihi, ilo))
                 }