diff options
| author | Prashanth Mundkur | 2018-05-03 15:47:03 -0700 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-05-03 15:48:01 -0700 |
| commit | e3b5d15bf2f48449fd43029fa1e0ca9270ec481d (patch) | |
| tree | 7bc7a6efe312648b67f5d512858095a8306cc070 /riscv/riscv_step.sail | |
| parent | c4af140507927c924065c5d32235f258b200a203 (diff) | |
Simplify the top-level execute loop using the step function.
Diffstat (limited to 'riscv/riscv_step.sail')
| -rw-r--r-- | riscv/riscv_step.sail | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/riscv/riscv_step.sail b/riscv/riscv_step.sail index e670e2b8..b5d8e897 100644 --- a/riscv/riscv_step.sail +++ b/riscv/riscv_step.sail @@ -43,12 +43,13 @@ function fetch() -> FetchResult = { val step : unit -> unit effect {barr, eamem, escape, exmem, rmem, rreg, wmv, wreg} function step() = { - tick_clock(); - match curInterrupt(mip, mie, mideleg) { - Some(intr, priv) => - handle_interrupt(intr, priv), + Some(intr, priv) => { + print_bits("\nHandling interrupt: ", intr); + handle_interrupt(intr, priv) + }, None() => { + print_bits("\nPC: ", PC); match fetch() { F_Error(e, addr) => handle_mem_exception(addr, e), F_RVC(h) => { |
