diff options
| author | Prashanth Mundkur | 2018-10-08 09:35:11 -0700 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-10-23 15:32:15 -0700 |
| commit | d43b475507ed9144b26be124376c3e656005a416 (patch) | |
| tree | 5d4bc4eba9b4993610ee9098abbd68c2cac01fe0 /riscv/riscv_step.sail | |
| parent | e3490924e6bce23d3d4b236fdc61c7345a17e814 (diff) | |
RISC-V: Add a platform knob to control mtval contents on illegal instruction faults.
Diffstat (limited to 'riscv/riscv_step.sail')
| -rw-r--r-- | riscv/riscv_step.sail | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/riscv/riscv_step.sail b/riscv/riscv_step.sail index f9675115..218be598 100644 --- a/riscv/riscv_step.sail +++ b/riscv/riscv_step.sail @@ -63,7 +63,8 @@ function step(step_no) = { match decodeCompressed(h) { None() => { print("[" ^ string_of_int(step_no) ^ "] [" ^ cur_privilege ^ "]: " ^ BitStr(PC) ^ " (" ^ BitStr(h) ^ ") <no-decode>"); - handle_decode_exception(EXTZ(h)); + instbits = EXTZ(h); + handle_illegal(); (false, true) }, Some(ast) => { @@ -77,7 +78,8 @@ function step(step_no) = { match decode(w) { None() => { print("[" ^ string_of_int(step_no) ^ "] [" ^ cur_privilege ^ "]: " ^ BitStr(PC) ^ " (" ^ BitStr(w) ^ ") <no-decode>"); - handle_decode_exception(EXTZ(w)); + instbits = EXTZ(w); + handle_illegal(); (false, true) }, Some(ast) => { |