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authorPrashanth Mundkur2018-06-11 16:15:14 -0700
committerPrashanth Mundkur2018-06-11 16:15:14 -0700
commitce3a0880a46b3ed59a0e875173bbc9a0899892eb (patch)
tree123f2e816dedbdb8d04bdfd7f731d43e78a8720f /riscv/riscv_step.sail
parentbe54131898dcf13b9f10da55bd3175d84ff99ae4 (diff)
Use riscv platform insns_per_tick to tick the clock.
Diffstat (limited to 'riscv/riscv_step.sail')
-rw-r--r--riscv/riscv_step.sail23
1 files changed, 14 insertions, 9 deletions
diff --git a/riscv/riscv_step.sail b/riscv/riscv_step.sail
index 36f633ef..73343029 100644
--- a/riscv/riscv_step.sail
+++ b/riscv/riscv_step.sail
@@ -41,9 +41,10 @@ function fetch() -> FetchResult = {
}
}
-/* returns whether an instruction was executed */
-val step : int -> bool effect {barr, eamem, escape, exmem, rmem, rreg, wmv, wreg}
-function step(step_no) = {
+/* returns whether an instruction was retired */
+val step : unit -> bool effect {barr, eamem, escape, exmem, rmem, rreg, wmv, wreg}
+function step() = {
+ let step_no = unsigned(minstret);
match curInterrupt(mip, mie, mideleg) {
Some(intr, priv) => {
print_bits("Handling interrupt: ", intr);
@@ -91,17 +92,14 @@ function step(step_no) = {
val loop : int -> unit effect {barr, eamem, escape, exmem, rmem, rreg, wmv, wreg}
function loop (tohost_addr) = {
- let tohost = __GetSlice_int(64, tohost_addr, 0);
+ let insns_per_tick = plat_insns_per_tick();
i : int = 0;
while true do {
tick_clock();
minstret_written = false; /* see note for minstret */
- let retired = step(i);
+ let retired = step();
PC = nextPC;
- if retired then {
- i = i + 1;
- retire_instruction()
- };
+ if retired then retire_instruction();
/* check htif exit */
if htif_done then {
@@ -109,6 +107,13 @@ function loop (tohost_addr) = {
if exit_val == 0 then print("SUCCESS")
else print_int("FAILURE: ", exit_val);
exit(());
+ };
+
+ /* update time */
+ i = i + 1;
+ if i == insns_per_tick then {
+ tick_clock();
+ i = 0;
}
}
}