diff options
| author | Prashanth Mundkur | 2018-05-03 15:02:08 -0700 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-05-03 15:02:08 -0700 |
| commit | c4af140507927c924065c5d32235f258b200a203 (patch) | |
| tree | 8ae74895e7789666e582ea52b52791d6987a3b4c /riscv/riscv_step.sail | |
| parent | e39941e0ddf924502d17dc55f94fe09f1e4494d0 (diff) | |
Fix up interrupt and exception dispatch.
Diffstat (limited to 'riscv/riscv_step.sail')
| -rw-r--r-- | riscv/riscv_step.sail | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/riscv/riscv_step.sail b/riscv/riscv_step.sail index ca0e102a..e670e2b8 100644 --- a/riscv/riscv_step.sail +++ b/riscv/riscv_step.sail @@ -46,9 +46,8 @@ function step() = { tick_clock(); match curInterrupt(mip, mie, mideleg) { - Some(intr, priv) => { - () - }, + Some(intr, priv) => + handle_interrupt(intr, priv), None() => { match fetch() { F_Error(e, addr) => handle_mem_exception(addr, e), |