Fix riscv interrupt pending check to handle implicit enabling at lower privileges.

Also fix timer threshold comparison to be <= instead of <.

1 files changed, 1 insertions, 1 deletions

diff --git a/riscv/riscv_step.sail b/riscv/riscv_step.sail
index fe9d7e84..49f8e51c 100644
--- a/riscv/riscv_step.sail
+++ b/riscv/riscv_step.sail
@@ -44,7 +44,7 @@ function fetch() -> FetchResult = {
 /* returns whether an instruction was retired */
 val step : int -> bool effect {barr, eamem, escape, exmem, rmem, rreg, wmv, wreg}
 function step(step_no) = {
-  match curInterrupt(mip, mie, mideleg) {
+  match curInterrupt(cur_privilege, mip, mie, mideleg) {
     Some(intr, priv) => {
       print_bits("Handling interrupt: ", intr);
       handle_interrupt(intr, priv);