Some more riscv trace log tweaking for spike compatibility.

1 files changed, 6 insertions, 4 deletions

diff --git a/riscv/riscv_step.sail b/riscv/riscv_step.sail
index de823f53..acbab1f6 100644
--- a/riscv/riscv_step.sail
+++ b/riscv/riscv_step.sail
@@ -42,9 +42,8 @@ function fetch() -> FetchResult = {
 }
 
 /* returns whether an instruction was retired */
-val step : unit -> bool effect {barr, eamem, escape, exmem, rmem, rreg, wmv, wreg}
-function step() = {
-  let step_no = unsigned(minstret);
+val step : int -> bool effect {barr, eamem, escape, exmem, rmem, rreg, wmv, wreg}
+function step(step_no) = {
   match curInterrupt(mip, mie, mideleg) {
     Some(intr, priv) => {
       print_bits("Handling interrupt: ", intr);
@@ -94,13 +93,16 @@ val loop : unit -> unit effect {barr, eamem, escape, exmem, rmem, rreg, wmv, wre
 function loop () = {
   let insns_per_tick = plat_insns_per_tick();
   i : int = 0;
+  step_no : int = 0;
   while true do {
     tick_clock();
     minstret_written = false;     /* see note for minstret */
-    let retired = step();
+    let retired = step(step_no);
     PC = nextPC;
     if retired then retire_instruction();
 
+    step_no = step_no + 1;
+
     /* check htif exit */
     if htif_done then {
       let exit_val = unsigned(htif_exit_code);