diff options
| author | Jon French | 2018-11-01 15:58:08 +0000 |
|---|---|---|
| committer | Jon French | 2018-11-01 15:58:08 +0000 |
| commit | 6bab4056ba7cd10e0dc633187b74b24a73bdd259 (patch) | |
| tree | 9d9b6fb1f26122b6fa1a1a86359737c928b9991b /riscv/riscv_platform_impl.h | |
| parent | d47313c00011be39ed1c2e411d401bb759ed65bf (diff) | |
| parent | 29f69b03602552d3ca1a29713527d21f5790e28a (diff) | |
Merge branch 'sail2' into rmem_interpreter
Diffstat (limited to 'riscv/riscv_platform_impl.h')
| -rw-r--r-- | riscv/riscv_platform_impl.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/riscv/riscv_platform_impl.h b/riscv/riscv_platform_impl.h new file mode 100644 index 00000000..85e25c95 --- /dev/null +++ b/riscv/riscv_platform_impl.h @@ -0,0 +1,28 @@ +#pragma once + +#include <stdbool.h> +#include <stdint.h> + +/* Settings of the platform implementation. */ + +#define DEFAULT_RSTVEC 0x00001000 +#define SAIL_XLEN 64 + +extern bool rv_enable_dirty_update; +extern bool rv_enable_misaligned; +extern bool rv_mtval_has_illegal_inst_bits; + +extern uint64_t rv_ram_base; +extern uint64_t rv_ram_size; + +extern uint64_t rv_rom_base; +extern uint64_t rv_rom_size; + +extern uint64_t rv_clint_base; +extern uint64_t rv_clint_size; + +extern uint64_t rv_htif_tohost; +extern uint64_t rv_insns_per_tick; + +extern int term_fd; +void plat_term_write_impl(char c); |
