RISC-V: Add some debug logs for within_phys_mem.

1 files changed, 6 insertions, 0 deletions

diff --git a/riscv/riscv_platform.c b/riscv/riscv_platform.c
index 31ec09c4..be926f6a 100644
--- a/riscv/riscv_platform.c
+++ b/riscv/riscv_platform.c
@@ -13,31 +13,37 @@ bool plat_enable_misaligned_access(unit u)
 
 mach_bits plat_ram_base(unit u)
 {
+  fprintf(stderr, "plat_ram_base: -> %0" PRIx64 "\n", rv_ram_base);
   return rv_ram_base;
 }
 
 mach_bits plat_ram_size(unit u)
 {
+  fprintf(stderr, "plat_ram_size: -> %0" PRIx64 "\n", rv_ram_size);
   return rv_rom_base;
 }
 
 mach_bits plat_rom_base(unit u)
 {
+  fprintf(stderr, "plat_rom_base: -> %0" PRIx64 "\n", rv_rom_base);
   return rv_rom_base;
 }
 
 mach_bits plat_rom_size(unit u)
 {
+  fprintf(stderr, "plat_rom_size: -> %0" PRIx64 "\n", rv_rom_size);
   return rv_rom_size;
 }
 
 mach_bits plat_clint_base(unit u)
 {
+  fprintf(stderr, "plat_clint_base: -> %0" PRIx64 "\n", rv_clint_base);
   return rv_clint_base;
 }
 
 mach_bits plat_clint_size(unit u)
 {
+  fprintf(stderr, "plat_clint_size: -> %0" PRIx64 "\n", rv_clint_size);
   return rv_clint_size;
 }