diff options
| author | Prashanth Mundkur | 2018-10-08 09:35:11 -0700 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-10-23 15:32:15 -0700 |
| commit | d43b475507ed9144b26be124376c3e656005a416 (patch) | |
| tree | 5d4bc4eba9b4993610ee9098abbd68c2cac01fe0 /riscv/riscv_extras_sequential.lem | |
| parent | e3490924e6bce23d3d4b236fdc61c7345a17e814 (diff) | |
RISC-V: Add a platform knob to control mtval contents on illegal instruction faults.
Diffstat (limited to 'riscv/riscv_extras_sequential.lem')
| -rw-r--r-- | riscv/riscv_extras_sequential.lem | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/riscv/riscv_extras_sequential.lem b/riscv/riscv_extras_sequential.lem index a6fa1298..7028d5b8 100644 --- a/riscv/riscv_extras_sequential.lem +++ b/riscv/riscv_extras_sequential.lem @@ -97,6 +97,10 @@ val plat_enable_misaligned_access : unit -> bool let plat_enable_misaligned_access () = false declare ocaml target_rep function plat_enable_misaligned_access = `Platform.enable_misaligned_access` +val plat_mtval_has_illegal_inst_bits : unit -> bool +let plat_mtval_has_illegal_inst_bits () = false +declare ocaml target_rep function plat_mtval_has_illegal_inst_bits = `Platform.mtval_has_illegal_inst_bits` + val plat_insns_per_tick : unit -> integer let plat_insns_per_tick () = 1 declare ocaml target_rep function plat_insns_per_tick = `Platform.insns_per_tick` |