diff options
| author | Jon French | 2018-07-05 13:09:41 +0100 |
|---|---|---|
| committer | Jon French | 2018-07-05 13:09:46 +0100 |
| commit | c080665a6fbd8c88b66440a7bddc31a9634741cf (patch) | |
| tree | bbd54114de4afe2abea9e7b4e7b1bf9e103b8eaa /riscv/riscv_extras_sequential.lem | |
| parent | eb306a0d3e3abc96d5227b9f240666c5bff6869f (diff) | |
restore missing RISC-V fence types in sail2; ignore io bits in fences more cleanly
Diffstat (limited to 'riscv/riscv_extras_sequential.lem')
| -rw-r--r-- | riscv/riscv_extras_sequential.lem | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/riscv/riscv_extras_sequential.lem b/riscv/riscv_extras_sequential.lem index 601f5008..b29fe545 100644 --- a/riscv/riscv_extras_sequential.lem +++ b/riscv/riscv_extras_sequential.lem @@ -13,6 +13,10 @@ let MEM_fence_r_rw () = barrier Barrier_RISCV_r_rw let MEM_fence_r_r () = barrier Barrier_RISCV_r_r let MEM_fence_rw_w () = barrier Barrier_RISCV_rw_w let MEM_fence_w_w () = barrier Barrier_RISCV_w_w +let MEM_fence_w_rw () = barrier Barrier_RISCV_w_rw +let MEM_fence_rw_r () = barrier Barrier_RISCV_rw_r +let MEM_fence_r_w () = barrier Barrier_RISCV_r_w +let MEM_fence_w_r () = barrier Barrier_RISCV_w_r let MEM_fence_i () = barrier Barrier_RISCV_i val MEMea : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e |