print to stdout not stderr to stop upsetting rmem regression tests

1 files changed, 7 insertions, 1 deletions

diff --git a/riscv/riscv_extras_sequential.lem b/riscv/riscv_extras_sequential.lem
index b29fe545..b3d84df6 100644
--- a/riscv/riscv_extras_sequential.lem
+++ b/riscv/riscv_extras_sequential.lem
@@ -101,7 +101,13 @@ val shift_bits_left : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvecto
 let shift_bits_left v m = shiftl v (uint m)
 
 val print_string : string -> string -> unit
-let print_string msg s = prerr_endline (msg ^ s)
+let print_string msg s = print_endline (msg ^ s)
+
+val prerr_string : string -> string -> unit
+let prerr_string msg s = prerr_endline (msg ^ s)
 
 val prerr_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit
 let prerr_bits msg bs = prerr_endline (msg ^ (show_bitlist (bits_of bs)))
+
+val print_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit
+let print_bits msg bs = print_endline (msg ^ (show_bitlist (bits_of bs)))