diff options
| author | Prashanth Mundkur | 2018-01-29 06:02:48 -0800 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-01-29 06:39:38 -0800 |
| commit | f206ae0ab7ff4e1870a002db2c9e2f030244ce31 (patch) | |
| tree | 46b5b9f478c6968265bed23ae7510d461b96c7f0 /riscv/prelude.sail | |
| parent | 5a33eab7bc05f45cde76253f84e139b2428fbbe7 (diff) | |
Added ecall/mret and exception support.
Diffstat (limited to 'riscv/prelude.sail')
| -rw-r--r-- | riscv/prelude.sail | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/riscv/prelude.sail b/riscv/prelude.sail index 427da759..69fc1017 100644 --- a/riscv/prelude.sail +++ b/riscv/prelude.sail @@ -331,6 +331,7 @@ union exception = { Error_not_implemented : string, Error_misaligned_access, Error_EBREAK, + Error_internal_error } val "sign_extend" : forall 'n 'm, 'm >= 'n. (bits('n), atom('m)) -> bits('m) @@ -373,3 +374,12 @@ val operator << = "shift_bits_left" : forall 'n 'm. (bits('n), bits('m)) -> bits val vector64 : int -> bits(64) function vector64 n = __raw_GetSlice_int(64, n, 0) + +val vector_update_subrange_dec = "update_subrange" : forall 'n 'm 'o. + (bits('n), atom('m), atom('o), bits('m - ('o - 1))) -> bits('n) + +val vector_update_subrange_inc = "update_subrange" : forall 'n 'm 'o. + (vector('n, inc, bit), atom('m), atom('o), vector('o - ('m - 1), inc, bit)) -> vector('n, inc, bit) + +overload vector_update_subrange = {vector_update_subrange_dec, vector_update_subrange_inc} + |