diff options
| author | Prashanth Mundkur | 2018-04-20 17:35:48 -0700 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-04-20 17:36:49 -0700 |
| commit | 1b95665db9cf1deda3bfe243ed4038c47d1e940f (patch) | |
| tree | edc696c04df6634925d78fa0c18af6d29f3dc802 /riscv/prelude.sail | |
| parent | 8d74837e5b95866ed24795e81d1e685499067cfa (diff) | |
Add a riscv instruction printer for the execution log.
Diffstat (limited to 'riscv/prelude.sail')
| -rw-r--r-- | riscv/prelude.sail | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/prelude.sail b/riscv/prelude.sail index d90d7f2c..2051c7fa 100644 --- a/riscv/prelude.sail +++ b/riscv/prelude.sail @@ -169,7 +169,7 @@ val int_power = {ocaml: "int_power", lem: "pow"} : (int, int) -> int val real_power = {ocaml: "real_power", lem: "realPowInteger"} : (real, int) -> real -overload operator ^ = {xor_vec, int_power, real_power} +overload operator ^ = {xor_vec, int_power, real_power, concat_str} val add_range = {ocaml: "add_int", lem: "integerAdd"} : forall 'n 'm 'o 'p. (range('n, 'm), range('o, 'p)) -> range('n + 'o, 'm + 'p) |