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authorPrashanth Mundkur2018-11-21 14:02:18 -0800
committerPrashanth Mundkur2018-11-21 14:19:21 -0800
commit01a6e9b8ad00728fdbf12a76cda24144a75ec552 (patch)
tree2026fcadd803d41fb1aac4a8de7f4b1a71a94c07 /riscv/platform_main.ml
parentb5cdd319822f9b2836a3bccf827121cb7ab0a105 (diff)
RISC-V: allow platform ram size to be configurable.
Diffstat (limited to 'riscv/platform_main.ml')
-rw-r--r--riscv/platform_main.ml3
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/platform_main.ml b/riscv/platform_main.ml
index b33247f1..1c9ba209 100644
--- a/riscv/platform_main.ml
+++ b/riscv/platform_main.ml
@@ -76,6 +76,9 @@ let options = Arg.align ([("-dump-dts",
("-mtval-has-illegal-inst-bits",
Arg.Set P.config_mtval_has_illegal_inst_bits,
" mtval stores instruction bits on an illegal instruction exception");
+ ("-ram-size",
+ Arg.Int PI.set_dram_size,
+ " size of physical ram memory to use (in MB)");
("-with-dtc",
Arg.String PI.set_dtc,
" full path to dtc to use")