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| author | Prashanth Mundkur | 2018-06-07 12:53:53 -0700 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-06-07 13:08:53 -0700 |
| commit | b96a2672bebac3331c539ddbffaa678f43704d5f (patch) | |
| tree | 54609d279e4a41567cbb93d10d17189f2ed80123 /riscv/platform.ml | |
| parent | 23dd87e399b619bb040d6d965fe9d61e604ae517 (diff) | |
More definitions for the physical memory map.
Diffstat (limited to 'riscv/platform.ml')
| -rw-r--r-- | riscv/platform.ml | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/riscv/platform.ml b/riscv/platform.ml index 485acb76..15b28abb 100644 --- a/riscv/platform.ml +++ b/riscv/platform.ml @@ -74,6 +74,12 @@ let rom_size () = bits_of_int !rom_size_ref let dram_base () = bits_of_int64 P.dram_base let dram_size () = bits_of_int64 P.dram_size +let htif_tohost () = + bits_of_int64 (Big_int.to_int64 (Elf.elf_tohost ())) + +let clint_base () = bits_of_int64 P.clint_base +let clint_size () = bits_of_int64 P.clint_size + (* terminal I/O *) let term_write char_bits = let big_char = Big_int.bitwise_and (uint char_bits) (Big_int.of_int 255) in |
