Make riscv pte dirty-bit update handling configurable via a platform cli option.

Fix a redundant clock tick.

1 files changed, 5 insertions, 0 deletions

diff --git a/riscv/platform.ml b/riscv/platform.ml
index 0aac4884..1b3ecf5d 100644
--- a/riscv/platform.ml
+++ b/riscv/platform.ml
@@ -52,6 +52,9 @@ open Sail_lib;;
 module P = Platform_impl;;
 module Elf = Elf_loader;;
 
+(* Platform configuration *)
+let config_enable_dirty_update = ref false
+
 (* Mapping to Sail externs *)
 
 let bits_of_int i =
@@ -75,6 +78,8 @@ let make_rom start_pc =
      *)
     rom )
 
+let enable_dirty_update () = !config_enable_dirty_update
+
 let rom_base () = bits_of_int64 P.rom_base
 let rom_size () = bits_of_int   !rom_size_ref