diff options
| author | Prashanth Mundkur | 2018-11-21 14:02:18 -0800 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-11-21 14:19:21 -0800 |
| commit | 01a6e9b8ad00728fdbf12a76cda24144a75ec552 (patch) | |
| tree | 2026fcadd803d41fb1aac4a8de7f4b1a71a94c07 /riscv/platform.ml | |
| parent | b5cdd319822f9b2836a3bccf827121cb7ab0a105 (diff) | |
RISC-V: allow platform ram size to be configurable.
Diffstat (limited to 'riscv/platform.ml')
| -rw-r--r-- | riscv/platform.ml | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/platform.ml b/riscv/platform.ml index 06486ca2..f2e9f7b6 100644 --- a/riscv/platform.ml +++ b/riscv/platform.ml @@ -69,7 +69,7 @@ let bits_of_int64 i = let rom_size_ref = ref 0 let make_rom start_pc = let reset_vec = List.concat (List.map P.uint32_to_bytes (P.reset_vec_int start_pc)) in - let dtb = P.make_dtb P.dts in + let dtb = P.make_dtb (P.make_dts ()) in let rom = reset_vec @ dtb in ( rom_size_ref := List.length rom; (* @@ -89,7 +89,7 @@ let rom_base () = bits_of_int64 P.rom_base let rom_size () = bits_of_int !rom_size_ref let dram_base () = bits_of_int64 P.dram_base -let dram_size () = bits_of_int64 P.dram_size +let dram_size () = bits_of_int64 !P.dram_size_ref let htif_tohost () = bits_of_int64 (Big_int.to_int64 (Elf.elf_tohost ())) |