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| author | Christopher Pulte | 2017-08-22 14:39:33 +0100 |
|---|---|---|
| committer | Christopher Pulte | 2017-08-22 14:39:33 +0100 |
| commit | cef2b0b20414ece1e1ebe957c4149e5c786c5245 (patch) | |
| tree | 784881b0bbbdcdb7acb185dfd291a30604c0a175 /risc-v/riscv_extras_embed_sequential.lem | |
| parent | d8c238ddac07ed8bf828596ff68198d0c63758f5 (diff) | |
| parent | 6cc248cc27d9133e23da1454f115176f0799a572 (diff) | |
Merge branch 'master' of https://bitbucket.org/Peter_Sewell/sail
Diffstat (limited to 'risc-v/riscv_extras_embed_sequential.lem')
| -rw-r--r-- | risc-v/riscv_extras_embed_sequential.lem | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/risc-v/riscv_extras_embed_sequential.lem b/risc-v/riscv_extras_embed_sequential.lem index 93b5dfec..0fca7709 100644 --- a/risc-v/riscv_extras_embed_sequential.lem +++ b/risc-v/riscv_extras_embed_sequential.lem @@ -37,10 +37,14 @@ let MEMval_conditional_release (_,_,v) = write_mem_val v >>= fun b -> return (if val MEM_fence_rw_rw : unit -> M unit val MEM_fence_r_rw : unit -> M unit val MEM_fence_rw_w : unit -> M unit +val MEM_fence_w_w : unit -> M unit +val MEM_fence_i : unit -> M unit let MEM_fence_rw_rw () = barrier Barrier_RISCV_rw_rw let MEM_fence_r_rw () = barrier Barrier_RISCV_r_rw let MEM_fence_rw_w () = barrier Barrier_RISCV_rw_w +let MEM_fence_w_w () = barrier Barrier_RISCV_w_w +let MEM_fence_i () = barrier Barrier_RISCV_i let duplicate (bit,len) = let bits = repeat [bit] len in |