diff options
| author | Shaked Flur | 2017-11-01 14:17:08 +0000 |
|---|---|---|
| committer | Shaked Flur | 2017-11-01 14:17:08 +0000 |
| commit | 8e5d44d17c71cf946e65e15de8df42de2af4c652 (patch) | |
| tree | b3611980594a34c65475887377e4afb55a983526 /risc-v/riscv_extras_embed_sequential.lem | |
| parent | 701d572adda905e6b2098a73c9af56f98212b4a3 (diff) | |
added RISC-V "fence r,r"
Diffstat (limited to 'risc-v/riscv_extras_embed_sequential.lem')
| -rw-r--r-- | risc-v/riscv_extras_embed_sequential.lem | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/risc-v/riscv_extras_embed_sequential.lem b/risc-v/riscv_extras_embed_sequential.lem index 1f2a0e47..3c922268 100644 --- a/risc-v/riscv_extras_embed_sequential.lem +++ b/risc-v/riscv_extras_embed_sequential.lem @@ -53,12 +53,14 @@ let speculate_conditional_success () = excl_result () >>= fun b -> return (if b val MEM_fence_rw_rw : unit -> M unit val MEM_fence_r_rw : unit -> M unit +val MEM_fence_r_r : unit -> M unit val MEM_fence_rw_w : unit -> M unit val MEM_fence_w_w : unit -> M unit val MEM_fence_i : unit -> M unit let MEM_fence_rw_rw () = barrier Barrier_RISCV_rw_rw let MEM_fence_r_rw () = barrier Barrier_RISCV_r_rw +let MEM_fence_r_r () = barrier Barrier_RISCV_r_r let MEM_fence_rw_w () = barrier Barrier_RISCV_rw_w let MEM_fence_w_w () = barrier Barrier_RISCV_w_w let MEM_fence_i () = barrier Barrier_RISCV_i |