added RISC-V load-acquire

12 files changed, 36 insertions, 20 deletions

diff --git a/risc-v/hgen/ast.hgen b/risc-v/hgen/ast.hgen
index 8983b5ae..6e323e85 100644
--- a/risc-v/hgen/ast.hgen
+++ b/risc-v/hgen/ast.hgen
@@ -5,7 +5,7 @@
 | `RISCVIType of bit12 * reg * reg * riscvIop
 | `RISCVShiftIop of bit6 * reg * reg * riscvSop
 | `RISCVRType of reg * reg * reg * riscvRop
-| `RISCVLoad of bit12 * reg * reg * bool * wordWidth
+| `RISCVLoad of bit12 * reg * reg * bool * wordWidth * bool
 | `RISCVStore of bit12 * reg * reg * wordWidth
 | `RISCVADDIW of bit12 * reg * reg
 | `RISCVSHIFTW of bit5 * reg * reg * riscvSop
diff --git a/risc-v/hgen/fold.hgen b/risc-v/hgen/fold.hgen
index 03318805..be91659b 100644
--- a/risc-v/hgen/fold.hgen
+++ b/risc-v/hgen/fold.hgen
@@ -6,7 +6,7 @@
 | `RISCVIType (_, r0, r1, _)      -> fold_reg r0 (fold_reg r1 (y_reg, y_sreg))
 | `RISCVShiftIop (_, r0, r1, _)   -> fold_reg r0 (fold_reg r1 (y_reg, y_sreg))
 | `RISCVRType (r0, r1, r2, _)     -> fold_reg r0 (fold_reg r1 (fold_reg r2 (y_reg, y_sreg)))
-| `RISCVLoad (_, r0, r1, _, _)    -> fold_reg r0 (fold_reg r1 (y_reg, y_sreg))
+| `RISCVLoad (_, r0, r1, _, _, _) -> fold_reg r0 (fold_reg r1 (y_reg, y_sreg))
 | `RISCVStore (_, r0, r1, _)      -> fold_reg r0 (fold_reg r1 (y_reg, y_sreg))
 | `RISCVADDIW (_, r0, r1)         -> fold_reg r0 (fold_reg r1 (y_reg, y_sreg))
 | `RISCVSHIFTW (_, r0, r1, _)     -> fold_reg r0 (fold_reg r1 (y_reg, y_sreg))
diff --git a/risc-v/hgen/herdtools_ast_to_shallow_ast.hgen b/risc-v/hgen/herdtools_ast_to_shallow_ast.hgen
index 50026612..0e8bfdc2 100644
--- a/risc-v/hgen/herdtools_ast_to_shallow_ast.hgen
+++ b/risc-v/hgen/herdtools_ast_to_shallow_ast.hgen
@@ -30,12 +30,13 @@
       translate_reg "rs1" rs1,
       translate_reg "rd" rd,
       translate_rop op)
-| `RISCVLoad(imm, rs, rd, unsigned, width) -> LOAD(
+| `RISCVLoad(imm, rs, rd, unsigned, width, aq) -> LOAD(
       translate_imm12 "imm" imm,
       translate_reg "rs" rs,
       translate_reg "rd" rd,
       translate_bool "unsigned" unsigned,
-      translate_wordWidth width)
+      translate_wordWidth width,
+      translate_bool "aq" aq)
 | `RISCVStore(imm, rs, rd, width) -> STORE (
       translate_imm12 "imm" imm,
       translate_reg "rs" rs,
diff --git a/risc-v/hgen/lexer.hgen b/risc-v/hgen/lexer.hgen
index 5f2c8326..c4408139 100644
--- a/risc-v/hgen/lexer.hgen
+++ b/risc-v/hgen/lexer.hgen
@@ -33,13 +33,21 @@
 "or",   RTYPE{op=RISCVOR};
 "and",  RTYPE{op=RISCVAND};
 
-"lb",  LOAD{unsigned=false; width=RISCVBYTE};
-"lbu", LOAD{unsigned=true;  width=RISCVBYTE};
-"lh",  LOAD{unsigned=false; width=RISCVHALF};
-"lhu", LOAD{unsigned=true;  width=RISCVHALF};
-"lw",  LOAD{unsigned=false; width=RISCVWORD};
-"lwu", LOAD{unsigned=true;  width=RISCVWORD};
-"ld",  LOAD{unsigned=false; width=RISCVDOUBLE};
+"lb",  LOAD{unsigned=false; width=RISCVBYTE;   aq=false};
+"lbu", LOAD{unsigned=true;  width=RISCVBYTE;   aq=false};
+"lh",  LOAD{unsigned=false; width=RISCVHALF;   aq=false};
+"lhu", LOAD{unsigned=true;  width=RISCVHALF;   aq=false};
+"lw",  LOAD{unsigned=false; width=RISCVWORD;   aq=false};
+"lwu", LOAD{unsigned=true;  width=RISCVWORD;   aq=false};
+"ld",  LOAD{unsigned=false; width=RISCVDOUBLE; aq=false};
+
+"lb.aq",  LOAD{unsigned=false; width=RISCVBYTE;   aq=true};
+"lbu.aq", LOAD{unsigned=true;  width=RISCVBYTE;   aq=true};
+"lh.aq",  LOAD{unsigned=false; width=RISCVHALF;   aq=true};
+"lhu.aq", LOAD{unsigned=true;  width=RISCVHALF;   aq=true};
+"lw.aq",  LOAD{unsigned=false; width=RISCVWORD;   aq=true};
+"lwu.aq", LOAD{unsigned=true;  width=RISCVWORD;   aq=true};
+"ld.aq",  LOAD{unsigned=false; width=RISCVDOUBLE; aq=true};
 
 "sb", STORE{width=RISCVBYTE};
 "sh", STORE{width=RISCVHALF};
diff --git a/risc-v/hgen/map.hgen b/risc-v/hgen/map.hgen
index ff14c428..1deacc06 100644
--- a/risc-v/hgen/map.hgen
+++ b/risc-v/hgen/map.hgen
@@ -5,7 +5,7 @@
 | `RISCVIType (x, r0, r1, y)      -> `RISCVIType (x, map_reg r0, map_reg r1, y)
 | `RISCVShiftIop (x, r0, r1, y)   -> `RISCVShiftIop (x, map_reg r0, map_reg r1, y)
 | `RISCVRType (r0, r1, r2, y)     -> `RISCVRType (r0, map_reg r1, map_reg r2, y)
-| `RISCVLoad (x, r0, r1, y, z)    -> `RISCVLoad (x, map_reg r0, map_reg r1, y, z)
+| `RISCVLoad (x, r0, r1, y, z, a) -> `RISCVLoad (x, map_reg r0, map_reg r1, y, z, a)
 | `RISCVStore (x, r0, r1, y)      -> `RISCVStore (x, map_reg r0, map_reg r1, y)
 | `RISCVADDIW (x, r0, r1)         -> `RISCVADDIW (x, map_reg r0, map_reg r1)
 | `RISCVSHIFTW (x, r0, r1, y)     -> `RISCVSHIFTW (x, map_reg r0, map_reg r1, y)
diff --git a/risc-v/hgen/parser.hgen b/risc-v/hgen/parser.hgen
index 37fd8d8d..10257ecd 100644
--- a/risc-v/hgen/parser.hgen
+++ b/risc-v/hgen/parser.hgen
@@ -13,7 +13,7 @@
 | RTYPE reg COMMA reg COMMA reg
   { `RISCVRType ($6, $4, $2, $1.op) }
 | LOAD reg COMMA NUM LPAR reg RPAR
-  { `RISCVLoad($4, $6, $2, $1.unsigned, $1.width) }
+  { `RISCVLoad($4, $6, $2, $1.unsigned, $1.width, $1.aq) }
 | STORE reg COMMA NUM LPAR reg RPAR
   { `RISCVStore($4, $2, $6, $1.width) }
 | ADDIW reg COMMA reg COMMA NUM
diff --git a/risc-v/hgen/pretty.hgen b/risc-v/hgen/pretty.hgen
index 1da3ef11..6c4f3e53 100644
--- a/risc-v/hgen/pretty.hgen
+++ b/risc-v/hgen/pretty.hgen
@@ -7,7 +7,8 @@
 | `RISCVIType(imm, rs2, rs1, op)  -> sprintf "%s %s, %s, %d" (pp_riscv_iop op) (pp_reg rs1) (pp_reg rs2) imm
 | `RISCVShiftIop(imm, rs, rd, op) -> sprintf "%s %s, %s, %d" (pp_riscv_sop op) (pp_reg rd) (pp_reg rs) imm
 | `RISCVRType (rs2, rs1, rd, op)  -> sprintf "%s %s, %s, %s" (pp_riscv_rop op) (pp_reg rd) (pp_reg rs1) (pp_reg rs2)
-| `RISCVLoad(imm, rs, rd, unsigned, width) -> sprintf "%s %s, %d(%s)" (pp_riscv_load_op (unsigned, width)) (pp_reg rd) imm (pp_reg rs)
+| `RISCVLoad(imm, rs, rd, unsigned, width, aq)
+                                  -> sprintf "%s %s, %d(%s)" (pp_riscv_load_op (unsigned, width, aq)) (pp_reg rd) imm (pp_reg rs)
 | `RISCVStore(imm, rs2, rs1, width) -> sprintf "%s %s, %d(%s)" (pp_riscv_store_op width) (pp_reg rs2) imm (pp_reg rs1)
 | `RISCVADDIW(imm, rs, rd)        -> sprintf "addiw %s, %s, %d" (pp_reg rd) (pp_reg rs) imm
 | `RISCVSHIFTW(imm, rs, rd, op)   -> sprintf "%s %s, %s, %d" (pp_riscv_sop op) (pp_reg rd) (pp_reg rs) imm
diff --git a/risc-v/hgen/sail_trans_out.hgen b/risc-v/hgen/sail_trans_out.hgen
index dca5bea1..2a161bda 100644
--- a/risc-v/hgen/sail_trans_out.hgen
+++ b/risc-v/hgen/sail_trans_out.hgen
@@ -6,7 +6,8 @@
 | ("ITYPE", [imm; rs1; rd; op])   -> `RISCVIType(translate_out_simm12 imm, translate_out_ireg rs1, translate_out_ireg rd, translate_out_iop op)
 | ("SHIFTIOP", [imm; rs; rd; op]) -> `RISCVShiftIop(translate_out_imm6 imm, translate_out_ireg rs, translate_out_ireg rd, translate_out_sop op)
 | ("RTYPE", [rs2; rs1; rd; op])   -> `RISCVRType (translate_out_ireg rs2, translate_out_ireg rs1, translate_out_ireg rd, translate_out_rop op)
-| ("LOAD", [imm; rs; rd; unsigned; width]) -> `RISCVLoad(translate_out_simm12 imm, translate_out_ireg rs, translate_out_ireg rd, translate_out_bool unsigned, translate_out_wordWidth width)
+| ("LOAD", [imm; rs; rd; unsigned; width; aq])
+                                  -> `RISCVLoad(translate_out_simm12 imm, translate_out_ireg rs, translate_out_ireg rd, translate_out_bool unsigned, translate_out_wordWidth width, translate_out_bool aq)
 | ("STORE", [imm; rs; rd; width]) -> `RISCVStore(translate_out_simm12 imm, translate_out_ireg rs, translate_out_ireg rd, translate_out_wordWidth width)
 | ("ADDIW", [imm; rs; rd])        -> `RISCVADDIW(translate_out_simm12 imm, translate_out_ireg rs, translate_out_ireg rd)
 | ("SHIFTW", [imm; rs; rd; op])   -> `RISCVSHIFTW(translate_out_imm5 imm, translate_out_ireg rs, translate_out_ireg rd, translate_out_sop op)
diff --git a/risc-v/hgen/shallow_ast_to_herdtools_ast.hgen b/risc-v/hgen/shallow_ast_to_herdtools_ast.hgen
index 6158ebd7..c24ecd8f 100644
--- a/risc-v/hgen/shallow_ast_to_herdtools_ast.hgen
+++ b/risc-v/hgen/shallow_ast_to_herdtools_ast.hgen
@@ -6,7 +6,8 @@
 | ITYPE( imm, rs1, rd, op)    -> `RISCVIType(translate_out_simm12 imm, translate_out_ireg rs1, translate_out_ireg rd, translate_out_iop op)
 | SHIFTIOP( imm, rs, rd, op)  -> `RISCVShiftIop(translate_out_imm6 imm, translate_out_ireg rs, translate_out_ireg rd, translate_out_sop op)
 | RTYPE( rs2, rs1, rd, op)    -> `RISCVRType (translate_out_ireg rs2, translate_out_ireg rs1, translate_out_ireg rd, translate_out_rop op)
-| LOAD( imm, rs, rd, unsigned, width) -> `RISCVLoad(translate_out_simm12 imm, translate_out_ireg rs, translate_out_ireg rd, translate_out_bool unsigned, translate_out_wordWidth width)
+| LOAD( imm, rs, rd, unsigned, width, aq)
+                              -> `RISCVLoad(translate_out_simm12 imm, translate_out_ireg rs, translate_out_ireg rd, translate_out_bool unsigned, translate_out_wordWidth width, translate_out_bool aq)
 | STORE( imm, rs, rd, width)  -> `RISCVStore(translate_out_simm12 imm, translate_out_ireg rs, translate_out_ireg rd, translate_out_wordWidth width)
 | ADDIW( imm, rs, rd)         -> `RISCVADDIW(translate_out_simm12 imm, translate_out_ireg rs, translate_out_ireg rd)
 | SHIFTW( imm, rs, rd, op)    -> `RISCVSHIFTW(translate_out_imm5 imm, translate_out_ireg rs, translate_out_ireg rd, translate_out_sop op)
diff --git a/risc-v/hgen/token_types.hgen b/risc-v/hgen/token_types.hgen
index 2980b985..ca19c6eb 100644
--- a/risc-v/hgen/token_types.hgen
+++ b/risc-v/hgen/token_types.hgen
@@ -5,7 +5,7 @@ type token_BType    = {op : riscvBop }
 type token_IType    = {op : riscvIop }
 type token_ShiftIop = {op : riscvSop }
 type token_RTYPE    = {op : riscvRop }
-type token_Load     = {unsigned: bool; width : wordWidth }
+type token_Load     = {unsigned: bool; width : wordWidth; aq: bool }
 type token_Store    = {width : wordWidth }
 type token_ADDIW    = unit
 type token_SHIFTW   = {op : riscvSop }
diff --git a/risc-v/hgen/trans_sail.hgen b/risc-v/hgen/trans_sail.hgen
index df22d9dc..7fdfd516 100644
--- a/risc-v/hgen/trans_sail.hgen
+++ b/risc-v/hgen/trans_sail.hgen
@@ -58,7 +58,7 @@
       translate_rop "op" op;
     ],
     [])
-| `RISCVLoad(imm, rs, rd, unsigned, width) -> 
+| `RISCVLoad(imm, rs, rd, unsigned, width, aq) ->
    ("LOAD",
     [
       translate_imm12 "imm" imm;
@@ -66,6 +66,7 @@
       translate_reg "rd" rd;
       translate_bool "unsigned" unsigned;
       translate_width "width" width;
+      translate_bool "aq" aq;
     ],
     [])
 | `RISCVStore(imm, rs2, rs1, width) -> 
diff --git a/risc-v/hgen/types.hgen b/risc-v/hgen/types.hgen
index 87fc9b95..bb6d164c 100644
--- a/risc-v/hgen/types.hgen
+++ b/risc-v/hgen/types.hgen
@@ -99,7 +99,8 @@ type wordWidth =
   | RISCVWORD
   | RISCVDOUBLE
 
-let pp_riscv_load_op (unsigned, width) = match (unsigned, width) with
+let pp_riscv_load_op (unsigned, width, aq) =
+  begin match (unsigned, width) with
   | (false, RISCVBYTE)    -> "lb"
   | (true,  RISCVBYTE)    -> "lbu"
   | (false, RISCVHALF)    -> "lh"
@@ -107,7 +108,9 @@ let pp_riscv_load_op (unsigned, width) = match (unsigned, width) with
   | (false, RISCVWORD)    -> "lw"
   | (true,  RISCVWORD)    -> "lwu"
   | (_, RISCVDOUBLE)      -> "ld"
-  | _                          -> failwith "unexpected load op"
+  | _                     -> failwith "unexpected load op"
+  end
+  ^ (if aq then ".aq" else "")
 
 let pp_riscv_store_op width = match width with
 | RISCVBYTE -> "sb"