added RISCV_ prefix to some values to stop Lem from renaming them

2 files changed, 64 insertions, 64 deletions

diff --git a/risc-v/hgen/herdtools_types_to_shallow_types.hgen b/risc-v/hgen/herdtools_types_to_shallow_types.hgen
index a63f9aed..e6edd24d 100644
--- a/risc-v/hgen/herdtools_types_to_shallow_types.hgen
+++ b/risc-v/hgen/herdtools_types_to_shallow_types.hgen
@@ -4,48 +4,48 @@ let translate_reg name value =
     Sail_values.to_vec0 is_inc (Nat_big_num.of_int 5,Nat_big_num.of_int (reg_to_int value))
 
 let translate_uop op = match op with
-  | RISCVLUI   -> LUI0
-  | RISCVAUIPC -> AUIPC
+  | RISCVLUI   -> RISCV_LUI
+  | RISCVAUIPC -> RISCV_AUIPC
 
 let translate_bop op = match op with
-  | RISCVBEQ  -> BEQ0
-  | RISCVBNE  -> BNE
-  | RISCVBLT  -> BLT
-  | RISCVBGE  -> BGE
-  | RISCVBLTU -> BLTU
-  | RISCVBGEU -> BGEU
+  | RISCVBEQ  -> RISCV_BEQ
+  | RISCVBNE  -> RISCV_BNE
+  | RISCVBLT  -> RISCV_BLT
+  | RISCVBGE  -> RISCV_BGE
+  | RISCVBLTU -> RISCV_BLTU
+  | RISCVBGEU -> RISCV_BGEU
 
 let translate_iop op = match op with
-  | RISCVADDI  -> ADDI0 
-  | RISCVSLTI  -> SLTI0
-  | RISCVSLTIU -> SLTIU0
-  | RISCVXORI  -> XORI0
-  | RISCVORI   -> ORI0
-  | RISCVANDI  -> ANDI0
+  | RISCVADDI  -> RISCV_ADDI
+  | RISCVSLTI  -> RISCV_SLTI
+  | RISCVSLTIU -> RISCV_SLTIU
+  | RISCVXORI  -> RISCV_XORI
+  | RISCVORI   -> RISCV_ORI
+  | RISCVANDI  -> RISCV_ANDI
 
 let translate_sop op = match op with
-  | RISCVSLLI -> SLLI
-  | RISCVSRLI -> SRLI
-  | RISCVSRAI -> SRAI
+  | RISCVSLLI -> RISCV_SLLI
+  | RISCVSRLI -> RISCV_SRLI
+  | RISCVSRAI -> RISCV_SRAI
 
 let translate_rop op = match op with
-  | RISCVADD  -> ADD0 
-  | RISCVSUB  -> SUB0 
-  | RISCVSLL  -> SLL0 
-  | RISCVSLT  -> SLT0 
-  | RISCVSLTU -> SLTU0
-  | RISCVXOR  -> XOR0 
-  | RISCVSRL  -> SRL0 
-  | RISCVSRA  -> SRA0 
-  | RISCVOR   -> OR0  
-  | RISCVAND  -> AND0 
+  | RISCVADD  -> RISCV_ADD
+  | RISCVSUB  -> RISCV_SUB
+  | RISCVSLL  -> RISCV_SLL
+  | RISCVSLT  -> RISCV_SLT
+  | RISCVSLTU -> RISCV_SLTU
+  | RISCVXOR  -> RISCV_XOR
+  | RISCVSRL  -> RISCV_SRL
+  | RISCVSRA  -> RISCV_SRA
+  | RISCVOR   -> RISCV_OR
+  | RISCVAND  -> RISCV_AND
 
 let translate_ropw op = match op with
-  | RISCVADDW -> ADDW 
-  | RISCVSUBW -> SUBW 
-  | RISCVSLLW -> SLLW 
-  | RISCVSRLW -> SRLW 
-  | RISCVSRAW -> SRAW 
+  | RISCVADDW -> RISCV_ADDW
+  | RISCVSUBW -> RISCV_SUBW
+  | RISCVSLLW -> RISCV_SLLW
+  | RISCVSRLW -> RISCV_SRLW
+  | RISCVSRAW -> RISCV_SRAW
 
 let translate_amoop op = match op with
   | RISCVAMOSWAP -> AMOSWAP
diff --git a/risc-v/hgen/shallow_types_to_herdtools_types.hgen b/risc-v/hgen/shallow_types_to_herdtools_types.hgen
index 03b8820c..6b3b7f51 100644
--- a/risc-v/hgen/shallow_types_to_herdtools_types.hgen
+++ b/risc-v/hgen/shallow_types_to_herdtools_types.hgen
@@ -10,48 +10,48 @@ let translate_out_signed_int inst bits =
 let translate_out_ireg ireg = IReg (int_to_ireg (translate_out_int ireg))
 
 let translate_out_uop op = match op with
-  | LUI0  -> RISCVLUI  
-  | AUIPC -> RISCVAUIPC
+  | RISCV_LUI   -> RISCVLUI
+  | RISCV_AUIPC -> RISCVAUIPC
 
 let translate_out_bop op = match op with
-  | BEQ0 -> RISCVBEQ 
-  | BNE  -> RISCVBNE 
-  | BLT  -> RISCVBLT 
-  | BGE  -> RISCVBGE 
-  | BLTU -> RISCVBLTU
-  | BGEU -> RISCVBGEU
+  | RISCV_BEQ  -> RISCVBEQ
+  | RISCV_BNE  -> RISCVBNE
+  | RISCV_BLT  -> RISCVBLT
+  | RISCV_BGE  -> RISCVBGE
+  | RISCV_BLTU -> RISCVBLTU
+  | RISCV_BGEU -> RISCVBGEU
 
 let translate_out_iop op = match op with
-  | ADDI0  -> RISCVADDI 
-  | SLTI0  -> RISCVSLTI 
-  | SLTIU0 -> RISCVSLTIU
-  | XORI0  -> RISCVXORI 
-  | ORI0   -> RISCVORI  
-  | ANDI0  -> RISCVANDI 
+  | RISCV_ADDI   -> RISCVADDI
+  | RISCV_SLTI   -> RISCVSLTI
+  | RISCV_SLTIU  -> RISCVSLTIU
+  | RISCV_XORI   -> RISCVXORI
+  | RISCV_ORI    -> RISCVORI
+  | RISCV_ANDI   -> RISCVANDI
 
 let translate_out_sop op = match op with
-  | SLLI -> RISCVSLLI
-  | SRLI -> RISCVSRLI
-  | SRAI -> RISCVSRAI
+  | RISCV_SLLI -> RISCVSLLI
+  | RISCV_SRLI -> RISCVSRLI
+  | RISCV_SRAI -> RISCVSRAI
 
 let translate_out_rop op = match op with
-  | ADD0  -> RISCVADD 
-  | SUB0  -> RISCVSUB 
-  | SLL0  -> RISCVSLL 
-  | SLT0  -> RISCVSLT 
-  | SLTU0 -> RISCVSLTU
-  | XOR0  -> RISCVXOR 
-  | SRL0  -> RISCVSRL 
-  | SRA0  -> RISCVSRA 
-  | OR0   -> RISCVOR  
-  | AND0  -> RISCVAND 
+  | RISCV_ADD   -> RISCVADD
+  | RISCV_SUB   -> RISCVSUB
+  | RISCV_SLL   -> RISCVSLL
+  | RISCV_SLT   -> RISCVSLT
+  | RISCV_SLTU  -> RISCVSLTU
+  | RISCV_XOR   -> RISCVXOR
+  | RISCV_SRL   -> RISCVSRL
+  | RISCV_SRA   -> RISCVSRA
+  | RISCV_OR    -> RISCVOR
+  | RISCV_AND   -> RISCVAND
 
 let translate_out_ropw op = match op with
-  | ADDW  -> RISCVADDW
-  | SUBW  -> RISCVSUBW
-  | SLLW  -> RISCVSLLW
-  | SRLW  -> RISCVSRLW
-  | SRAW  -> RISCVSRAW
+  | RISCV_ADDW  -> RISCVADDW
+  | RISCV_SUBW  -> RISCVSUBW
+  | RISCV_SLLW  -> RISCVSLLW
+  | RISCV_SRLW  -> RISCVSRLW
+  | RISCV_SRAW  -> RISCVSRAW
 
 let translate_out_amoop op = match op with
   | AMOSWAP -> RISCVAMOSWAP