RISC-V store-release

12 files changed, 33 insertions, 20 deletions

diff --git a/risc-v/hgen/ast.hgen b/risc-v/hgen/ast.hgen
index 6e323e85..d5e4b45b 100644
--- a/risc-v/hgen/ast.hgen
+++ b/risc-v/hgen/ast.hgen
@@ -6,7 +6,7 @@
 | `RISCVShiftIop of bit6 * reg * reg * riscvSop
 | `RISCVRType of reg * reg * reg * riscvRop
 | `RISCVLoad of bit12 * reg * reg * bool * wordWidth * bool
-| `RISCVStore of bit12 * reg * reg * wordWidth
+| `RISCVStore of bit12 * reg * reg * wordWidth * bool
 | `RISCVADDIW of bit12 * reg * reg
 | `RISCVSHIFTW of bit5 * reg * reg * riscvSop
 | `RISCVRTYPEW of reg * reg * reg * riscvRopw
diff --git a/risc-v/hgen/fold.hgen b/risc-v/hgen/fold.hgen
index be91659b..376ab19f 100644
--- a/risc-v/hgen/fold.hgen
+++ b/risc-v/hgen/fold.hgen
@@ -7,7 +7,7 @@
 | `RISCVShiftIop (_, r0, r1, _)   -> fold_reg r0 (fold_reg r1 (y_reg, y_sreg))
 | `RISCVRType (r0, r1, r2, _)     -> fold_reg r0 (fold_reg r1 (fold_reg r2 (y_reg, y_sreg)))
 | `RISCVLoad (_, r0, r1, _, _, _) -> fold_reg r0 (fold_reg r1 (y_reg, y_sreg))
-| `RISCVStore (_, r0, r1, _)      -> fold_reg r0 (fold_reg r1 (y_reg, y_sreg))
+| `RISCVStore (_, r0, r1, _, _)   -> fold_reg r0 (fold_reg r1 (y_reg, y_sreg))
 | `RISCVADDIW (_, r0, r1)         -> fold_reg r0 (fold_reg r1 (y_reg, y_sreg))
 | `RISCVSHIFTW (_, r0, r1, _)     -> fold_reg r0 (fold_reg r1 (y_reg, y_sreg))
 | `RISCVRTYPEW (r0, r1, r2, _)    -> fold_reg r0 (fold_reg r1 (fold_reg r2 (y_reg, y_sreg)))
diff --git a/risc-v/hgen/herdtools_ast_to_shallow_ast.hgen b/risc-v/hgen/herdtools_ast_to_shallow_ast.hgen
index 0e8bfdc2..d756d3d0 100644
--- a/risc-v/hgen/herdtools_ast_to_shallow_ast.hgen
+++ b/risc-v/hgen/herdtools_ast_to_shallow_ast.hgen
@@ -37,11 +37,12 @@
       translate_bool "unsigned" unsigned,
       translate_wordWidth width,
       translate_bool "aq" aq)
-| `RISCVStore(imm, rs, rd, width) -> STORE (
+| `RISCVStore(imm, rs, rd, width, rl) -> STORE (
       translate_imm12 "imm" imm,
       translate_reg "rs" rs,
       translate_reg "rd" rd,
-      translate_wordWidth width)
+      translate_wordWidth width,
+      translate_bool "rl" rl)
 | `RISCVADDIW(imm, rs, rd) -> ADDIW(
       translate_imm12 "imm" imm,
       translate_reg "rs" rs,
diff --git a/risc-v/hgen/lexer.hgen b/risc-v/hgen/lexer.hgen
index c4408139..40481f75 100644
--- a/risc-v/hgen/lexer.hgen
+++ b/risc-v/hgen/lexer.hgen
@@ -49,10 +49,15 @@
 "lwu.aq", LOAD{unsigned=true;  width=RISCVWORD;   aq=true};
 "ld.aq",  LOAD{unsigned=false; width=RISCVDOUBLE; aq=true};
 
-"sb", STORE{width=RISCVBYTE};
-"sh", STORE{width=RISCVHALF};
-"sw", STORE{width=RISCVWORD};
-"sd", STORE{width=RISCVDOUBLE};
+"sb", STORE{width=RISCVBYTE;   rl=false};
+"sh", STORE{width=RISCVHALF;   rl=false};
+"sw", STORE{width=RISCVWORD;   rl=false};
+"sd", STORE{width=RISCVDOUBLE; rl=false};
+
+"sb.rl", STORE{width=RISCVBYTE;   rl=true};
+"sh.rl", STORE{width=RISCVHALF;   rl=true};
+"sw.rl", STORE{width=RISCVWORD;   rl=true};
+"sd.rl", STORE{width=RISCVDOUBLE; rl=true};
 
 "addiw", ADDIW ();
 
diff --git a/risc-v/hgen/map.hgen b/risc-v/hgen/map.hgen
index 1deacc06..edd376b4 100644
--- a/risc-v/hgen/map.hgen
+++ b/risc-v/hgen/map.hgen
@@ -6,7 +6,7 @@
 | `RISCVShiftIop (x, r0, r1, y)   -> `RISCVShiftIop (x, map_reg r0, map_reg r1, y)
 | `RISCVRType (r0, r1, r2, y)     -> `RISCVRType (r0, map_reg r1, map_reg r2, y)
 | `RISCVLoad (x, r0, r1, y, z, a) -> `RISCVLoad (x, map_reg r0, map_reg r1, y, z, a)
-| `RISCVStore (x, r0, r1, y)      -> `RISCVStore (x, map_reg r0, map_reg r1, y)
+| `RISCVStore (x, r0, r1, y, z)   -> `RISCVStore (x, map_reg r0, map_reg r1, y, z)
 | `RISCVADDIW (x, r0, r1)         -> `RISCVADDIW (x, map_reg r0, map_reg r1)
 | `RISCVSHIFTW (x, r0, r1, y)     -> `RISCVSHIFTW (x, map_reg r0, map_reg r1, y)
 | `RISCVRTYPEW (r0, r1, r2, x)    -> `RISCVRTYPEW (r0, map_reg r1, map_reg r2, x)
diff --git a/risc-v/hgen/parser.hgen b/risc-v/hgen/parser.hgen
index 10257ecd..cb31f5a9 100644
--- a/risc-v/hgen/parser.hgen
+++ b/risc-v/hgen/parser.hgen
@@ -15,7 +15,7 @@
 | LOAD reg COMMA NUM LPAR reg RPAR
   { `RISCVLoad($4, $6, $2, $1.unsigned, $1.width, $1.aq) }
 | STORE reg COMMA NUM LPAR reg RPAR
-  { `RISCVStore($4, $2, $6, $1.width) }
+  { `RISCVStore($4, $2, $6, $1.width, $1.rl) }
 | ADDIW reg COMMA reg COMMA NUM
   { `RISCVADDIW ($6, $4, $2) }
 | SHIFTW reg COMMA reg COMMA NUM
diff --git a/risc-v/hgen/pretty.hgen b/risc-v/hgen/pretty.hgen
index 6c4f3e53..cce77641 100644
--- a/risc-v/hgen/pretty.hgen
+++ b/risc-v/hgen/pretty.hgen
@@ -9,7 +9,8 @@
 | `RISCVRType (rs2, rs1, rd, op)  -> sprintf "%s %s, %s, %s" (pp_riscv_rop op) (pp_reg rd) (pp_reg rs1) (pp_reg rs2)
 | `RISCVLoad(imm, rs, rd, unsigned, width, aq)
                                   -> sprintf "%s %s, %d(%s)" (pp_riscv_load_op (unsigned, width, aq)) (pp_reg rd) imm (pp_reg rs)
-| `RISCVStore(imm, rs2, rs1, width) -> sprintf "%s %s, %d(%s)" (pp_riscv_store_op width) (pp_reg rs2) imm (pp_reg rs1)
+| `RISCVStore(imm, rs2, rs1, width, rl)
+                                  -> sprintf "%s %s, %d(%s)" (pp_riscv_store_op (width, rl)) (pp_reg rs2) imm (pp_reg rs1)
 | `RISCVADDIW(imm, rs, rd)        -> sprintf "addiw %s, %s, %d" (pp_reg rd) (pp_reg rs) imm
 | `RISCVSHIFTW(imm, rs, rd, op)   -> sprintf "%s %s, %s, %d" (pp_riscv_sop op) (pp_reg rd) (pp_reg rs) imm
 | `RISCVRTYPEW(rs2, rs1, rd, op)  -> sprintf "%s %s, %s, %s" (pp_riscv_ropw op) (pp_reg rd) (pp_reg rs1) (pp_reg rs2)
diff --git a/risc-v/hgen/sail_trans_out.hgen b/risc-v/hgen/sail_trans_out.hgen
index 2a161bda..45445a25 100644
--- a/risc-v/hgen/sail_trans_out.hgen
+++ b/risc-v/hgen/sail_trans_out.hgen
@@ -8,7 +8,8 @@
 | ("RTYPE", [rs2; rs1; rd; op])   -> `RISCVRType (translate_out_ireg rs2, translate_out_ireg rs1, translate_out_ireg rd, translate_out_rop op)
 | ("LOAD", [imm; rs; rd; unsigned; width; aq])
                                   -> `RISCVLoad(translate_out_simm12 imm, translate_out_ireg rs, translate_out_ireg rd, translate_out_bool unsigned, translate_out_wordWidth width, translate_out_bool aq)
-| ("STORE", [imm; rs; rd; width]) -> `RISCVStore(translate_out_simm12 imm, translate_out_ireg rs, translate_out_ireg rd, translate_out_wordWidth width)
+| ("STORE", [imm; rs; rd; width; rl])
+                                  -> `RISCVStore(translate_out_simm12 imm, translate_out_ireg rs, translate_out_ireg rd, translate_out_wordWidth width, translate_out_bool rl)
 | ("ADDIW", [imm; rs; rd])        -> `RISCVADDIW(translate_out_simm12 imm, translate_out_ireg rs, translate_out_ireg rd)
 | ("SHIFTW", [imm; rs; rd; op])   -> `RISCVSHIFTW(translate_out_imm5 imm, translate_out_ireg rs, translate_out_ireg rd, translate_out_sop op)
 | ("RTYPEW", [rs2; rs1; rd; op])  -> `RISCVRTYPEW(translate_out_ireg rs2, translate_out_ireg rs1, translate_out_ireg rd, translate_out_ropw op)
diff --git a/risc-v/hgen/shallow_ast_to_herdtools_ast.hgen b/risc-v/hgen/shallow_ast_to_herdtools_ast.hgen
index c24ecd8f..abfc0412 100644
--- a/risc-v/hgen/shallow_ast_to_herdtools_ast.hgen
+++ b/risc-v/hgen/shallow_ast_to_herdtools_ast.hgen
@@ -8,7 +8,8 @@
 | RTYPE( rs2, rs1, rd, op)    -> `RISCVRType (translate_out_ireg rs2, translate_out_ireg rs1, translate_out_ireg rd, translate_out_rop op)
 | LOAD( imm, rs, rd, unsigned, width, aq)
                               -> `RISCVLoad(translate_out_simm12 imm, translate_out_ireg rs, translate_out_ireg rd, translate_out_bool unsigned, translate_out_wordWidth width, translate_out_bool aq)
-| STORE( imm, rs, rd, width)  -> `RISCVStore(translate_out_simm12 imm, translate_out_ireg rs, translate_out_ireg rd, translate_out_wordWidth width)
+| STORE( imm, rs, rd, width, rl)
+                              -> `RISCVStore(translate_out_simm12 imm, translate_out_ireg rs, translate_out_ireg rd, translate_out_wordWidth width, translate_out_bool rl)
 | ADDIW( imm, rs, rd)         -> `RISCVADDIW(translate_out_simm12 imm, translate_out_ireg rs, translate_out_ireg rd)
 | SHIFTW( imm, rs, rd, op)    -> `RISCVSHIFTW(translate_out_imm5 imm, translate_out_ireg rs, translate_out_ireg rd, translate_out_sop op)
 | RTYPEW( rs2, rs1, rd, op)   -> `RISCVRTYPEW(translate_out_ireg rs2, translate_out_ireg rs1, translate_out_ireg rd, translate_out_ropw op)
diff --git a/risc-v/hgen/token_types.hgen b/risc-v/hgen/token_types.hgen
index ca19c6eb..03dde52b 100644
--- a/risc-v/hgen/token_types.hgen
+++ b/risc-v/hgen/token_types.hgen
@@ -6,7 +6,7 @@ type token_IType    = {op : riscvIop }
 type token_ShiftIop = {op : riscvSop }
 type token_RTYPE    = {op : riscvRop }
 type token_Load     = {unsigned: bool; width : wordWidth; aq: bool }
-type token_Store    = {width : wordWidth }
+type token_Store    = {width : wordWidth; rl: bool }
 type token_ADDIW    = unit
 type token_SHIFTW   = {op : riscvSop }
 type token_RTYPEW   = {op : riscvRopw }
diff --git a/risc-v/hgen/trans_sail.hgen b/risc-v/hgen/trans_sail.hgen
index 7fdfd516..9fb3b546 100644
--- a/risc-v/hgen/trans_sail.hgen
+++ b/risc-v/hgen/trans_sail.hgen
@@ -69,13 +69,14 @@
       translate_bool "aq" aq;
     ],
     [])
-| `RISCVStore(imm, rs2, rs1, width) -> 
+| `RISCVStore(imm, rs2, rs1, width, rl) ->
    ("STORE",
     [
       translate_imm12 "imm" imm;
       translate_reg "rs2" rs2;
       translate_reg "rs1" rs1;
       translate_width "width" width;
+      translate_bool "rl" rl;
     ],
     [])
 | `RISCVADDIW(imm, rs, rd)        -> 
diff --git a/risc-v/hgen/types.hgen b/risc-v/hgen/types.hgen
index 11d0921e..180e0b37 100644
--- a/risc-v/hgen/types.hgen
+++ b/risc-v/hgen/types.hgen
@@ -111,11 +111,14 @@ let pp_riscv_load_op (unsigned, width, aq) =
   end
   ^ (if aq then ".aq" else "")
 
-let pp_riscv_store_op width = match width with
-| RISCVBYTE -> "sb"
-| RISCVHALF -> "sh"
-| RISCVWORD -> "sw"
-| RISCVDOUBLE -> "sd"
+let pp_riscv_store_op (width, rl) =
+  begin match width with
+  | RISCVBYTE -> "sb"
+  | RISCVHALF -> "sh"
+  | RISCVWORD -> "sw"
+  | RISCVDOUBLE -> "sd"
+  end
+  ^ (if rl then ".rl" else "")
 
 let pp_riscv_fence_option = function
   | 0b0011 -> "rw"