added RISC-V "fence w,w" and "fence.i";

fixed the interpreter nias analysis;

10 files changed, 15 insertions, 1 deletions

diff --git a/risc-v/hgen/ast.hgen b/risc-v/hgen/ast.hgen
index a0a59e4a..6fd52b03 100644
--- a/risc-v/hgen/ast.hgen
+++ b/risc-v/hgen/ast.hgen
@@ -11,5 +11,6 @@
 | `RISCVSHIFTW of bit5 * reg * reg * riscvSop
 | `RISCVRTYPEW of reg * reg * reg * riscvRopw
 | `RISCVFENCE of bit4 * bit4
+| `RISCVFENCEI
 | `RISCVLoadRes of bool * bool * reg * wordWidth * reg
 | `RISCVStoreCon of bool * bool * reg * reg * wordWidth * reg
diff --git a/risc-v/hgen/herdtools_ast_to_shallow_ast.hgen b/risc-v/hgen/herdtools_ast_to_shallow_ast.hgen
index ffea1575..770f9263 100644
--- a/risc-v/hgen/herdtools_ast_to_shallow_ast.hgen
+++ b/risc-v/hgen/herdtools_ast_to_shallow_ast.hgen
@@ -60,6 +60,7 @@
 | `RISCVFENCE(pred, succ) -> FENCE(
       translate_imm4 "pred" pred,
       translate_imm4 "succ" succ)
+| `RISCVFENCEI -> FENCEI
 | `RISCVLoadRes(aq, rl, rs1, width, rd) -> LOADRES(
       translate_bool "aq" aq,
       translate_bool "rl" rl,
diff --git a/risc-v/hgen/lexer.hgen b/risc-v/hgen/lexer.hgen
index abc0ff82..d422e82f 100644
--- a/risc-v/hgen/lexer.hgen
+++ b/risc-v/hgen/lexer.hgen
@@ -75,6 +75,7 @@
 "r",  FENCEOPTION Fence_R;
 "w",  FENCEOPTION Fence_W;
 "rw", FENCEOPTION Fence_RW;
+"fence.i", FENCEI ();
 
 "lr.w",    LOADRES {width=RISCVWORD;   aq=false; rl=false};
 "lr.w.aq", LOADRES {width=RISCVWORD;   aq=true;  rl=false};
diff --git a/risc-v/hgen/parser.hgen b/risc-v/hgen/parser.hgen
index d077c2df..5b000725 100644
--- a/risc-v/hgen/parser.hgen
+++ b/risc-v/hgen/parser.hgen
@@ -27,13 +27,15 @@
     | (Fence_RW, Fence_RW) -> `RISCVFENCE (0b0011, 0b0011)
     | (Fence_R,  Fence_RW) -> `RISCVFENCE (0b0010, 0b0011)
     | (Fence_RW, Fence_W)  -> `RISCVFENCE (0b0011, 0b0001)
+    | (Fence_W,  Fence_W)  -> `RISCVFENCE (0b0001, 0b0001)
     | (Fence_RW, Fence_R)  -> failwith "'fence rw,r' is not supported"
     | (Fence_R,  Fence_R)  -> failwith "'fence r,r' is not supported"
     | (Fence_R,  Fence_W)  -> failwith "'fence r,w' is not supported"
     | (Fence_W,  Fence_RW) -> failwith "'fence w,rw' is not supported"
     | (Fence_W,  Fence_R)  -> failwith "'fence w,r' is not supported"
-    | (Fence_W,  Fence_W)  -> failwith "'fence w,w' is not supported"
   }
+| FENCEI
+  { `RISCVFENCEI }
 | LOADRES reg COMMA LPAR reg RPAR
   { `RISCVLoadRes($1.aq, $1.rl, $5, $1.width, $2) }
 | STORECON reg COMMA reg COMMA LPAR reg RPAR
diff --git a/risc-v/hgen/pretty.hgen b/risc-v/hgen/pretty.hgen
index b4516b16..0b6548ea 100644
--- a/risc-v/hgen/pretty.hgen
+++ b/risc-v/hgen/pretty.hgen
@@ -15,6 +15,7 @@
 | `RISCVSHIFTW(imm, rs, rd, op)   -> sprintf "%s %s, %s, %d" (pp_riscv_sop op) (pp_reg rd) (pp_reg rs) imm
 | `RISCVRTYPEW(rs2, rs1, rd, op)  -> sprintf "%s %s, %s, %s" (pp_riscv_ropw op) (pp_reg rd) (pp_reg rs1) (pp_reg rs2)
 | `RISCVFENCE(pred, succ)         -> sprintf "fence %s, %s" (pp_riscv_fence_option pred) (pp_riscv_fence_option succ)
+| `RISCVFENCEI                    -> sprintf "fence.i"
 | `RISCVLoadRes(aq, rl, rs1, width, rd)
                                   ->
                                     assert (rl = false);
diff --git a/risc-v/hgen/sail_trans_out.hgen b/risc-v/hgen/sail_trans_out.hgen
index f216180a..61477f43 100644
--- a/risc-v/hgen/sail_trans_out.hgen
+++ b/risc-v/hgen/sail_trans_out.hgen
@@ -14,6 +14,7 @@
 | ("SHIFTW", [imm; rs; rd; op])   -> `RISCVSHIFTW(translate_out_imm5 imm, translate_out_ireg rs, translate_out_ireg rd, translate_out_sop op)
 | ("RTYPEW", [rs2; rs1; rd; op])  -> `RISCVRTYPEW(translate_out_ireg rs2, translate_out_ireg rs1, translate_out_ireg rd, translate_out_ropw op)
 | ("FENCE", [pred; succ])         -> `RISCVFENCE(translate_out_imm4 pred, translate_out_imm4 succ)
+| ("FENCEI", [])                  -> `RISCVFENCEI
 | ("LOADRES", [aq; rl; rs1; width; rd])
                                   -> `RISCVLoadRes(translate_out_bool aq, translate_out_bool rl, translate_out_ireg rs1, translate_out_wordWidth width, translate_out_ireg rd)
 | ("STORECON", [aq; rl; rs2; rs1; width; rd])
diff --git a/risc-v/hgen/shallow_ast_to_herdtools_ast.hgen b/risc-v/hgen/shallow_ast_to_herdtools_ast.hgen
index 01d8dded..f84ed1fa 100644
--- a/risc-v/hgen/shallow_ast_to_herdtools_ast.hgen
+++ b/risc-v/hgen/shallow_ast_to_herdtools_ast.hgen
@@ -14,6 +14,7 @@
 | SHIFTW( imm, rs, rd, op)    -> `RISCVSHIFTW(translate_out_imm5 imm, translate_out_ireg rs, translate_out_ireg rd, translate_out_sop op)
 | RTYPEW( rs2, rs1, rd, op)   -> `RISCVRTYPEW(translate_out_ireg rs2, translate_out_ireg rs1, translate_out_ireg rd, translate_out_ropw op)
 | FENCE( pred, succ)          -> `RISCVFENCE(translate_out_imm4 pred, translate_out_imm4 succ)
+| FENCEI                      -> `RISCVFENCEI
 | LOADRES( aq, rl, rs1, width, rd)
                               -> `RISCVLoadRes(translate_out_bool aq, translate_out_bool rl, translate_out_ireg rs1, translate_out_wordWidth width, translate_out_ireg rd)
 | STORECON( aq, rl, rs2, rs1, width, rd)
diff --git a/risc-v/hgen/token_types.hgen b/risc-v/hgen/token_types.hgen
index c0ef8445..242a7173 100644
--- a/risc-v/hgen/token_types.hgen
+++ b/risc-v/hgen/token_types.hgen
@@ -11,6 +11,7 @@ type token_ADDIW    = unit
 type token_SHIFTW   = {op : riscvSop }
 type token_RTYPEW   = {op : riscvRopw }
 type token_FENCE    = unit
+type token_FENCEI   = unit
 type token_LoadRes  = {width : wordWidth; aq: bool; rl: bool }
 type token_StoreCon = {width : wordWidth; aq: bool; rl: bool }
 
diff --git a/risc-v/hgen/tokens.hgen b/risc-v/hgen/tokens.hgen
index 1276fd68..449be0f0 100644
--- a/risc-v/hgen/tokens.hgen
+++ b/risc-v/hgen/tokens.hgen
@@ -12,5 +12,6 @@
 %token <RISCVHGenBase.token_RTYPEW>   RTYPEW  
 %token <RISCVHGenBase.token_FENCE>    FENCE
 %token <RISCVHGenBase.token_FENCEOPTION> FENCEOPTION
+%token <RISCVHGenBase.token_FENCEI>   FENCEI
 %token <RISCVHGenBase.token_LoadRes>  LOADRES
 %token <RISCVHGenBase.token_StoreCon> STORECON
diff --git a/risc-v/hgen/trans_sail.hgen b/risc-v/hgen/trans_sail.hgen
index 4d568fe8..6d10471c 100644
--- a/risc-v/hgen/trans_sail.hgen
+++ b/risc-v/hgen/trans_sail.hgen
@@ -112,6 +112,10 @@
      translate_imm4 "succ" succ;
   ], 
   [])
+| `RISCVFENCEI ->
+  ("FENCEI",
+  [],
+  [])
 | `RISCVLoadRes(aq, rl, rs1, width, rd) ->
    ("LOADRES",
     [