diff options
| author | Alasdair Armstrong | 2017-07-10 19:14:41 +0100 |
|---|---|---|
| committer | Alasdair Armstrong | 2017-07-10 19:14:41 +0100 |
| commit | 6e323bc2be0c15eb70fc71d6791881cf00c42184 (patch) | |
| tree | d3f7e5979246f24470cda594151ebe0a142a7848 /mips_new_tc/mips_insts.sail | |
| parent | 61e964c60edad9209ba7fb4671720099b51c8571 (diff) | |
Bugfixes and testing new checker on the MIPS spec
Diffstat (limited to 'mips_new_tc/mips_insts.sail')
| -rw-r--r-- | mips_new_tc/mips_insts.sail | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/mips_new_tc/mips_insts.sail b/mips_new_tc/mips_insts.sail index d127f6db..d85ba0a5 100644 --- a/mips_new_tc/mips_insts.sail +++ b/mips_new_tc/mips_insts.sail @@ -1544,9 +1544,9 @@ function clause execute (MTC0(rt, rd, sel, double)) = { case _ -> (SignalException(ResI)) } } - +(* function unit TLBWriteEntry((TLBIndexT) idx) = { - pagemask := EXTZ(TLBPageMask); (* XXX EXTZ here forces register read in ocaml shallow embedding *) + pagemask := (bit[16]) (EXTZ(TLBPageMask)); (* XXX EXTZ here forces register read in ocaml shallow embedding *) switch(pagemask) { case 0x0000 -> () case 0x0003 -> () @@ -1578,7 +1578,7 @@ function unit TLBWriteEntry((TLBIndexT) idx) = { ((TLBEntries[idx]).d1 ) := TLBEntryLo1.D; ((TLBEntries[idx]).v1 ) := TLBEntryLo1.V; } - +*) union ast member TLBWI function clause decode (0b010000 : 0b10000000000000000000 : 0b000010) = Some(TLBWI) function clause execute (TLBWI) = { |